hi5741 Intersil Corporation, hi5741 Datasheet
hi5741
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hi5741 Summary of contents
Page 1
... Data Sheet 14-Bit, 100MSPS, High Speed D/A Converter The HI5741 is a 14-bit, 100MSPS, D/A converter which is implemented in the Intersil BiCMOS 10V (HBC-10) process. Operating from +5V and -5.2V, the converter provides 20.48mA of full scale output current and includes an input data register and bandgap voltage reference. Low glitch energy and excellent frequency domain performance are achieved using a segmented architecture ...
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... 14-BIT D6 MASTER REGISTER D10 D11 D12 (MSB) D13 CLK AV AGND DV DGND HI5741 +5V HI5741 0.01µF DV (16) CC D13 D13 (MSB) (1) D12 (2) D12 D11 (3) D11 (24) CTRL AMP IN D10 (4) D10 (25) CTRL AMP OUT D9 ( (6) (26) REF OUT D7 D7 (7) D6 (21 (8) ...
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... Spurious Free Dynamic Range within a Window (Note 4) 3 HI5741 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Junction Temperature to -0.5V HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C CC Maximum Storage Temperature Range . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s +300°C (SOIC - Lead Tips Only -4.94V to -5.46V +4.75 to +5.25V ...
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... Sine Wave, to -3dB Loss (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) (Note 4) See Figure 1 (Note 4) See Figure 1 (Note 4) See Figure 1 (Note 4) See Figure 1 (Note 4) (Note 5) (Note 5) (Note 5) (Note 5) ±5%, V ± Internal, REF HI5741BI T = -40°C TO +85°C A MIN TYP MAX - ...
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... PD SETT FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM CLK t SU D13-D0 I OUT t PD FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 5 HI5741 50% ERROR BAND FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT t t PW1 PW2 HLD HLD ...
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... FIGURE 4. TYPICAL POWER DISSIPATION OVER TEMPERATURE 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0 5000 10,000 CODE FIGURE 6. TYPICAL INL PERFORMANCE -50 -40 -30 -20 - TEMPERATURE (°C) FIGURE 8. TYPICAL OFFSET CURRENT OVER TEMPERATURE 6 HI5741 -1.17 -1.18 -1.19 -1.20 -1.21 -1.22 -1.23 -1.24 -1.25 -1.26 -1. -50 -40 -30 -20 -10 FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER 0.8 0.5 0.25 0 -0.25 -0.5 -0.8 15,000 0 FIGURE 7. TYPICAL DNL PERFORMANCE 4.2 4.0 3.8 3.6 3.4 3.2 3 ...
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... CLK (MSPS) OUT FIGURE 12. SFDR 100 MSPS CLK (MHz) OUT FIGURE 14. SFDR HI5741 (Continued 100 OUT -72 -74 -76 -78 ...
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... Control amplifier out. Provides precision control of the current sources when connected to CTRL AMP IN such that I 26 REF OUT -1.23V (typical) bandgap reference voltage output. Can sink up to 500µ overdriven by an external reference capable of delivering up to 2mA. 8 HI5741 (Continued 100 MSPS MTPR = 75.17dBc CLK ...
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... Clocks and Termination The internal 14-bit register is updated on the rising edge of the clock. Since the HI5741 clock rate can run to 100 MSPS, to minimize reflections and clock noise into the part, proper termination should be used. In PCB layout clock runs should be kept short and have a minimum of loads ...
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... Settling Time The settling time of the HI5741 is measured as the time it takes for the output of the DAC to settle to within a ±defined error band of its final value during a 0001 0000.... or 1111... to 1110 1111...) scale transition. In defining settling time specifications for the HI5741, two levels of accuracy are considered ...
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... FIGURE 25. MEASURING GLITCH ENERGY Applications Bipolar Applications To convert the output of the HI5741 to a bipolar 4V swing, the following applications circuit is recommended. The reference can only provide 125µA of drive must be buffered to create the bipolar offset current needed to generate the -2V output with all bits ‘off’. The output current must be converted to a voltage and then gained up and offset to produce the proper swing ...
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... CLK BASEBAND BIT ENCODER STREAM CONTROLLER FIGURE 27. PSK MODULATOR USING THE HI5741 AND HSP45106 16-BIT NCO 12 HI5741 Multi-Tone Power Ratio (MTPR) is the amplitude difference from peak amplitude to peak distortion (either harmonic or the clock frequency is non-harmonic tone pattern is loaded into the D/A. The tone spacing of this pattern (∆ ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 HI5741 M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...