cs5422 ON Semiconductor, cs5422 Datasheet - Page 13

• Manufacturer Part Number: cs5422
• Description: Dual Outofphase Synchronous Buck Controller With Current Limit
• Manufacturer: ON Semiconductor

application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
determined by the following formula:
where:
switching MOSFET conduction losses can be calculated:
where:
MOSFET switch−on and switch−off and can be determined
by using the following formula:
where:
then be calculated as:
where:
P HFET(TOTAL) + P RMS(H) ) P SWH(ON) ) P SWH(OFF)
I RMS(H) +
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
The designer must ensure that the total power dissipation
The maximum RMS current through the switch can be
I
I
I
D = duty cycle.
Once the RMS current through the switch is known, the
P
I
R
The upper MOSFET switching losses are caused during
P
P
V
I
t
t
T = 1/f
The total power dissipation in the switching MOSFET can
P
P
P
RISE
FALL
RMS(H)
L(PEAK)
L(VALLEY)
RMS(H)
OUT
RMS(H)
SWH(ON)
SWH(OFF)
HFET(TOTAL)
RMS(H)
SWH(ON)
DS(ON)
IN
= input voltage;
= load current;
= MOSFET rise time (from FET manufacturer’s
= MOSFET fall time (from FET manufacturer’s
SW
switching characteristics performance curve);
P SWH + P SWH(ON) ) P SWH(OFF)
= maximum switching MOSFET RMS current;
= maximum switching MOSFET RMS current;
switching characteristics performance curve);
P RMS(H) + I RMS(H) 2
= switching MOSFET conduction losses;
= FET drain−to−source on−resistance
= upper MOSFET switch conduction Losses;
= inductor peak current;
= upper MOSFET switch−on losses;
= period.
= upper MOSFET switch−on losses;
= upper MOSFET switch−off losses;
= inductor valley current;
= total switching (upper) MOSFET losses;
+
I L(PEAK) 2 ) (I L(PEAK)
) I L(VALLEY) 2
V IN
I OUT
6T
(t RISE ) t FALL )
D
3
R DS(ON)
I L(VALLEY) )
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13
known, the maximum FET switch junction temperature can
be calculated:
where:
Selection of the Synchronous (Lower) FET
calculated as follows:
where:
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
where:
GATE(H)−to−GA TE(L) delay (from CS5422 data sheet
Electrical Characteristics section);
MOSFET can then be calculated as:
where:
is known the maximum FET switch junction temperature
can be calculated:
where:
P
Once the total power dissipation in the switching FET is
T
T
P
R
The switch conduction losses for the lower FET can be
P
I
D = Duty Cycle;
R
The synchronous MOSFET has no switching losses,
P
V
I
Non−overlap
f
The total power dissipation in the synchronous (lower)
P
P
P
Once the total power dissipation in the synchronous FET
T
T
P
R
P SWL + V SD
OUT
LOAD
SW
SWH(OFF)
A
HFET(TOTAL)
RMS(L)
SWL
LFET(TOTAL)
RMS(L)
SWL
A
LFET(TOTAL)
J
ΘJA
DS(ON)
J
ΘJA
SD
= FET junction temperature;
= MOSFET junction temperature;
P RMS(L) + I RMS 2
= ambient temperature;
= ambient temperature;
= switching frequency.
= lower FET source−to−drain voltage;
= load current;
= lower FET junction−to−ambient thermal resistance.
= upper FET junction−to−ambient thermal resistance.
= lower FET switching losses;
= Switching losses.
= load current;
T J + T A ) [P HFET(TOTAL)
T J + T A ) [P LFET(TOTAL)
P LFET(TOTAL) + P RMS(L) ) P SWL
= lower MOSFET conduction losses;
= Switch Conduction Losses;
= lower FET drain−to−source on−resistance.
= upper MOSFET switch−off losses;
+ [I OUT
= Synchronous (lower) FET total losses;
= total synchronous (lower) FET losses;
= total switching (upper) FET losses;
time
I LOAD
=
(1 * D) ] 2
R DS(ON)
GATE(L)−to−GA TE(H)
non−overlap time
R DS(ON)
R QJA ]
R QJA ]
f SW
or