ad1879 Analog Devices, Inc., ad1879 Datasheet - Page 11

• Manufacturer Part Number: ad1879
• Description: High Performance 16-/18-bit Stereo Adcs
• Manufacturer: Analog Devices, Inc.

At the other limit, if the word clock (WCK) is HI during the first
bit clock (BCK) of the field, then the MSB of the output word
will be valid on the rising edge of the 2nd bit clock (BCK) as
shown in Figure 12. The effect is to delay the MSB for one bit
clock cycle into the field, making the output data compatible at
the data format level with the I
REV. 0
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
DATA OUTPUT
WCK INPUT
WCK INPUT
WCK INPUT
LRCK I/O
LRCK I/O
BCK I/O
AD1878
LRCK I/O
Figure 10. AD1878 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 16th BCK
(Master Mode or Slave Mode)
BCK I/O
AD1879
AD1878
BCK I/O
AD1879
Figure 11. AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 14th BCK
(Master Mode or Slave Mode)
Figure 12. AD1878/AD1879 64-Bit Output Frame Timing with WCK as Input: WCK Hl During 1st BCK
(Master Mode or Slave Mode)
PREVIOUS DATA
LSB
Figure 13. AD1878/AD1879 32-Bit Output Frame Timing (Master Mode or Slave Mode)
PREVIOUS DATA
32
LSB
DATA OUTPUT
DATA OUTPUT
ZEROS
ZEROS
32
32
1
LRCK I/O
ZEROS
BCK I/O
AD1879
1
1
AD1878
ZEROS
LEFT DATA
LEFT DATA
MSB
MSB
2
2
2
MSB–1
MSB–1
3
3
3
16
2
S data format.
MSB
MSB
LSB–3
LSB–1
14
1
16
14
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LEFT DATA
LEFT DATA
LEFT DATA
15
LSB-2
MSB
LSB
2
15
17
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–1
16
3
16
18
LEFT DATA
MSB
17
4
LSB
17
19
MSB–1 MSB–2 MSB–3
18
5
18
20
ZEROS
ZEROS
19
6
21
19
20
LSB–3
LSB-1
22
20
15
LSB–2
LSB–1
LSB
–11–
16
LSB–1
31
31
31
MSB
MSB
LSB
LSB
32
In 64-bit frame modes with word clock (WCK) as an input, the
relative placement of the word clock (WCK) input can vary
from 32-bit field to 32-bit field, even within the same 64-bit
frame. For example, within a single 64-bit frame the left word
could be right-justified (by keeping WCK LO) and the right
word could be in an I
WCK HI at the beginning of the second field).
1
32
32
ZEROS
ZEROS
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
RIGHT DATA
RIGHT DATA
2
1
ZEROS
1
1
RIGHT DATA
RIGHT DATA
ZEROS
MSB
MSB
3
2
2
2
MSB–1
MSB–1
4
3
3
3
5
LSB–3
LSB–1
14
14
16
6
2
RIGHT DATA
S-compatible data format (by having
15
MSB
LSB-2
LSB
15
17
LSB–3 LSB–2
LSB-1
MSB–1 MSB–2 MSB–3 MSB–4 MSB–5
LSB–1
16
15
16
18
RIGHT DATA
LSB
MSB MSB–1 MSB–2 MSB–3
16
17
LSB
19
17
AD1878/AD1879
18
1
18
20
19
19
21
ZEROS
ZEROS
20
20
22
LSB–1
LSB–1
31
31
31
LSB
32
LSB
32
32
1
1
1