ad1843jst Analog Devices, Inc., ad1843jst Datasheet - Page 44

• Manufacturer Part Number: ad1843jst
• Description: Serial-port 16-bit Soundcomm Codec
• Manufacturer: Analog Devices, Inc.

AD1843
NTSC
Divisor
1
2
3
4
5
6
7
8
*When C3M6:4 = “100,” base frequency is 48,000 Hz only if NTSC sync rate is increased by 1001/1000, or is exactly 15.570 kHz.
PAL
Divisor
1
2
3
4
5
6
7
8
C3C15:0
Address 23
Data 15
C3C15
Data 7
C3C7
(C3M7 = “0”):
(C3M3:0)
(0000)
(0001)
(0010)
(0011)
(0100)
(0101)
(0110)
(0111)
Clock Generator 3 Conversion (Sample) Rate Select. Defines the conversion rate produced by Clock Generator 3
When in Video Lock Mode (C3REF and C3VID are both set to “1”):
Bits C3M7:0 select the Conversion clock rate. The most significant bit (C3M7) must be set to indicate the type of
video lock, either NTSC or PAL. For an NTSC lock, C3M7 must be reset to “0,” and the SYNC3 pin must
receive the NTSC sync frequency (525 lines/frame 30 Hz
C3M7 must be set to “1,” and the SYNC3 pin must receive the PAL sync frequency (625 lines/frame 25 Hz frame
rate
the least significant four bits (C3M3:0) select a divisor. The Conversion clock created by Clock Generator 3 will be
the base divided by the divisor. The following tables list the possible choices for base and divisor.
(C3M7 = “1”):
(C3M3:0)
(0000)
(0001)
(0010)
(0011)
(0100)
(0101)
(0110)
(0111)
Initial default state after reset: 0000 0000 1111 1111 (00FF hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
when not referenced to the SYNC3 pin (Control Register Address 22 Bit 15 [C3REF]). One LSB represents exactly
one Hertz, assuming a 24.576 MHz clock input on the XTALI pin. Usable range is 4 kHz (0x0FA0) to 54 kHz
(0xD2F0).
Initial default state after reset: 1011 1011 1000 0000 (BB80 hex), which is 48 kHz, assuming a 24.576 MHz clock in-
put on the XTALI pin. Cleared to default and cannot be written to when: the RESET pin is asserted LO; or when
the PWRDWN pin is asserted LO.
15.625 kHz). The next three most significant bits (C3M6:4) select a desired base Conversion clock rate, and
Data 14
C3C14
Data 6
C3C6
Base Frequency In Hz (C3M6:4)
48,000
(000)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Base Frequency In Hz (C3M6:4)
48,000
(000)
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Clock Generator 3 Control—Sample Rate
Data 13
C3C13
Data 5
C3C5
32,000
(001)
Yes
Yes
No
Yes
Yes
No
No
No
32,000
(001)
Yes
Yes
No
Yes
Yes
No
No
No
Data 12
C3C12
Data 4
C3C4
–44–
44,100
(010)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
44,100
(010)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data 11
C3C11
Data 3
C3C3
1000/1001 frame rate
44,100
(011)
Yes
Yes
No
Yes
Yes
No
No
No
44,100
(011)
Yes
Yes
No
Yes
Yes
No
No
No
Data 10
C3C10
Data 2
C3C2
2/3
2/3
48,000*
(100)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Data 9
Data 1
C3C9
C3C1
15.734 kHz). For a PAL lock,
Data 8
Data 0
44,056
(101)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
C3C8
C3C0
REV. 0