ad1848 Analog Devices, Inc., ad1848 Datasheet - Page 11

• Manufacturer Part Number: ad1848
• Description: Parallel-port 16-bit Soundport Stereo Codec
• Manufacturer: Analog Devices, Inc.

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CONTROL REGISTERS
Control Register Architecture
The AD1848K SoundPort Stereo Codec accepts both data and
control information through its byte-wide parallel port. Indirect
addressing minimizes the number of external pins required to
access all 21 of its byte-wide internal registers. Only two
external address pins, ADR1:0, are required to accomplish all
data and control transfers. These pins select one of five direct
registers. (ADR1:0 = 3 addresses two registers, depending on
whether the transfer is a playback or a capture.)
A write to or a read from the Indexed Data Register will access
the indirect register which is indexed by the value most recently
written to the Index Address Register. The Status Register and
the PIO Data Register are always accessible directly, without in-
dexing. The 16 indirect registers are indexed in Figure 5.
Direct Registers:
Indirect Registers:
Note that the only sticky bit in any of the AD1848K control registers is the interrupt (INT) bit. All other bits change with every
sample period.
IXA3:0
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Figure 4. AD1848K Direct Register Map
ADR1:0
0
1
2
3
ADR1:0
0
1
2
3
3
XCTL1
Data 7
DMA5
LMX1
RMX1
LMX2
RMX2
LDM
RDM
CPIO
LSS1
RSS1
COR
UB7
LB7
res
res
Register Name
Index Address Register
Indexed Data Register
Status Register
PIO Data Registers
Data 7
IXD7
CU/L
INIT
CD7
P D 7
XCTL0
Data 6
DMA4
PPIO
LSS0
RSS0
FMT
PUR
UB6
LB6
res
res
res
res
res
res
res
Data 6
IXD6
MCE
CL/R
CD6
P D 6
Figure 6. AD1848K Register Summary
Data 5
LMGE
RMGE
DMA3
LDA5
RDA5
UB5
LB5
Data 5
L/C
ACI
CRDY
IXD5
res
res
res
res
res
res
res
T RD
CD5
P D 5
LX1A4
RX1A4
LX2A4
RX2A4
Data 4
Data 4
DMA2
SOUR
LDA4
RDA4
–11–
IXD4
CD4
DRS
UB4
P D 4
LB4
S/M
res
res
res
res
res
res
A detailed map of all direct and indirect register contents is
summarized for reference as follows:
Data 3
IXD3
IXA3
PU/L
CD3
P D 3
LX1A3
RX1A3
LX2A3
RX2A3
Data 3
DMA1
LDA3
RDA3
ACAL
ORR1
LIG3
RIG3
CFS2
Figure 5. AD1848K Indirect Register Map
UB3
LB3
ID 3
res
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Data 2
IXD2
IXA2
PL/R
CD2
P D 2
LX1A2
RX1A2
LX2A2
RX2A2
Data 2
DMA0
LDA2
RDA2
ORR0
LIG2
RIG2
CFS1
SDC
UB2
LB2
Register Name
Left Input Control
Right Input Control
Left Aux #1 Input Control
Right Aux #1 Input Control
Left Aux #2 Input Control
Right Aux #2 Input Control
Left Output Control
Right Output Control
Clock and Data Format
Interface Configuration
Pin Control
Test and Initialization
Miscellaneous Information
Digital Mix
Upper Base Count
Lower Base Count
ID 2
res
Data 1
PRDY
IXD1
IXA1
CD1
P D 1
LX1A1
RX1A1
LX2A1
RX2A1
Data 1
LDA1
RDA1
ORL1
LIG1
RIG1
CFS0
CEN
UB1
IEN
LB1
ID 1
res
Data 0
IXD0
IXA0
CD0
AD1848K
IN T
P D 0
RX1A0
RX2A0
LX1A0
LX2A0
Data 0
LDA0
RDA0
ORL0
LIG0
RIG0
DME
PEN
UB0
CSS
LB0
ID 0
res