ad1859jrz Analog Devices, Inc., ad1859jrz Datasheet - Page 11

• Manufacturer Part Number: ad1859jrz
• Description: Stereo, Single-supply 18-bit Integrated Dac
• Manufacturer: Analog Devices, Inc.

REV. A
AD1859 has been designed to minimize pops and clicks when
muting and unmuting the device. The AD1859 includes a zero
crossing detector which attempts to implement attenuation
changes on waveform zero crossings only. If a zero crossing is
not found within 1024 input sample periods (approximately
23 ms at 44.1 kHz), the attenuation change is made regardless.
Output Drive, Buffering and Loading
The AD1859 analog output stage is able to drive a 2 k load. If
lower impedance loads must be driven, an external buffer stage
such as the Analog Devices SSM2142 should be used. The
analog output is generally ac coupled with a 10 F capacitor,
even if the optional de-emphasis circuit is not used, as shown in
Figure 17. It is possible to dc couple the AD1859 output into an
op amp stage using the CMOUT signal as a bias point.
On-Chip Voltage Reference
The AD1859 includes an on-chip voltage reference that estab-
lishes the output voltage range. The nominal value of this refer-
ence is +2.25 V which corresponds to a line output voltage
swing of 3 V p-p. The line output signal is centered around a
voltage established by the CMOUT (common mode) output
(Pin 1). The reference must be bypassed both on the FILT in-
put (Pin 28) with 10 F and 0.1 F capacitors, and on the
CMOUT output (Pin 1) with a 10 F and 0.1 F capacitors, as
shown in Figures 17 and 18. The FILT pin must use the
FGND ground, and the CMOUT pin must use the AGND
ground. The on-chip voltage reference may be overdriven with
an external reference source by applying this voltage to the
FILT pin. CMOUT and FILT must still be bypassed as shown
in Figures 17 and 18. An external reference can be useful to
calibrate multiple AD1859 DACs to the same gain. Reference
bypass capacitors larger than those suggested can be used to im-
prove the signal-to-noise performance of the AD1859.
Power Down and Reset
The PD/RST input (Pin 11) is used to control the power con-
sumed by the AD1859. When PD/RST is held LO, the AD1859
is placed in a low dissipation power-down state. When PD/RST
is brought HI, the AD1859 becomes ready for normal operation.
The master clock (XTALI/MCLK, Pin 16) must be running for
a successful reset or power-down operation to occur. The PD/RST
signal must be LO for a minimum of four master clock periods
(approximately 150 ns with a 27 MHz XTALI/MCLK
frequency).
When the PD/RST input (Pin 11) is asserted brought HI, the
AD1859 is reset. All registers in the AD1859 digital engine (se-
rial data port, interpolation filter and modulator) are zeroed, and
the amplifiers in the analog section are shorted during the reset
operation. The two registers in the serial control port are initial-
ized to their default values. The user should wait 100 ms after
bringing PD/RST HI before using the serial data input port and
the serial control input port in order for the digital phase locked
loop to re-acquire lock. The AD1859 has been designed to
minimize pops and clicks when entering and exiting the power-
down state.
Control Signals
The IDPM0, IDPM1, 18/16, and DEEMP control inputs are
normally connected HI or LO to establish the operating state of
the AD1859. They can be changed dynamically (and asynchro-
nously to the LRCLK and the master clock) as long as they are
stable before the first serial data input bit (i.e., the MSB) is pre-
sented to the AD1859.
–11–
APPLICATIONS ISSUES
Interface to MPEG Audio Decoders
Figure 11 shows the suggested interface to the Analog Devices
ADSP-21xx family of DSP chips, for which several MPEG
audio decode algorithms are available. The ADSP-21xx supports
16 bits of data using a left-justified DSP serial port style format.
Figure 12 shows the suggested interface to the Texas Instru-
ments TMS320AV110 MPEG audio decoder IC. The
TMS320AV110 supports 18 bits of data using a right-justified
output format.
Figure 13 shows the suggested interface to the LSI Logic L64111
MPEG audio decoder IC. The L64111 supports 16 bits of data
using a left-justified output format.
Figure 14 shows the suggested interface to the Philips SAA2500
MPEG audio decoder IC. The SAA2500 supports 18 bits of
data using an I
TMS320AV110
INSTRUMENTS
ADSP-21xx
LSI LOGIC
SAA2500
L64111
TEXAS
PHILIPS
Figure 12. Interface to TMS320AV110
Figure 11. Interface to ADSP-21xx
Figure 14. Interface to SAA2500
2
Figure 13. Interface to L64111
S compatible output format.
PCMDATA
FSCLKIN
LRCLKO
SYSCLK
PCMCLK
SCLKO
LRCLK
SERO
SCLK
SCLK
SCK
RFS
TFS
WS
SD
DR
DT
256 x F
384 x F
1536 x F
384 x F
512 x F
OR
48 x F
NC
NC
OR
TO
S
S
S
S
S
S
LO
LO
LO
LO
LO
HI
HI
HI
LO
HI
HI
HI
14
13
12
10
14
13
12
10
14
13
12
10
14
13
12
10
8
8
9
9
8
9
9
8
BCLK
LRCLK
SDATA
IDPM0
IDPM1
18/16
BCLK
LRCLK
SDATA
IDPM0
IDPM1
18/16
BCLK
LRCLK
SDATA
IDPM0
IDPM1
18/16
BCLK
LRCLK
SDATA
IDPM0
IDPM1
18/16
AD1859
AD1859
AD1859
AD1859
AD1859