adc11dv200cisqe National Semiconductor Corporation, adc11dv200cisqe Datasheet - Page 4

• Manufacturer Part Number: adc11dv200cisqe
• Description: Dual 11-bit, 200 Msps Low-power A/d Converter With Parallel Lvds/cmos Outputs
• Manufacturer: National Semiconductor Corporation

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DIGITAL I/O
LVDS Output Mode
Pin No.
24, 25
26, 27
28, 29
32, 33
34, 35
39, 40
41, 42
43, 44
47, 48
49, 50
51, 52
57
56
36
53
23
37
38
D10+, D10-
OUTSEL
D1+, D1-
D2+, D2-
D3+, D3-
D4+, D4-
D5+, D5-
D6+, D6-
D7+, D7-
D8+, D8-
D9+, D9-
D0+,D0-
Symbol
DRDY+
DRDY-
CLK +
CLK -
PD_A
PD_B
Equivalent Circuit
4
Clock input pins signal. The analog inputs are sampled on the
rising edge of this signal. The clock can be configured for
single-ended mode by shorting the CLK- pin to AGND. When
in differential mode, the common mode voltage for the clock
is internally set to 1.2V.
Two-state input controlling Power Down.
PD = V
reduced.
PD = AGND, Normal operation.
Two-state input controlling Output Mode.
OUTSEL = V
OUTSEL = AGND, CMOS Output Mode.
LVDS Output pairs for bits 0 through 10. A-channel and B-
channel digital LVDS outputs are interleaved. A channel is
ready at rising edge of DRDY and B channel is ready at the
falling edge of DRDY.
Data Ready Strobe. This signal is a LVDS DDR clock used to
capture the output data. A-channel data is valid on the rising
edge of this signal and B-channel data is valid on the falling
edge.
A
, Power Down is enabled and power dissipation is
D
, LVDS Output Mode.
Description