adc1173cimtcx National Semiconductor Corporation, adc1173cimtcx Datasheet - Page 17

• Manufacturer Part Number: adc1173cimtcx
• Description: 8-bit, 3-volt, 15msps, 33mw A/d Converter
• Manufacturer: National Semiconductor Corporation

If reference voltages are desired that are more than a few tens
of millivolts from the self-bias values, the circuit of Figure 5
will allow forcing the reference voltages to whatever levels are
desired. This circuit provides the best performance because
of the low source impedance of the transistors. Note that the
V
V
supply voltage, and V
and 1.0V below V
accurate conversions, the total reference voltage range (V
- V
V
V
the -5V points in Figure 5 can be returned to ground and the
negative supply eliminated.
3.0 POWER SUPPLY CONSIDERATIONS
Many A/D converters draw sufficient transient current to cor-
rupt their own power supplies if not adequately bypassed. A
10µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 centimeters) of the A/D power pins,
with a 0.1 µF ceramic chip capacitor placed as close as pos-
sible to the converter's power supply pins. Leadless chip
capacitors are preferred because they have low lead induc-
tance.
While a single voltage source should be used for the analog
and digital supplies of the ADC1173, these supply pins should
be well isolated from each other to prevent any digital noise
from being coupled to the analog power pins. A 47 Ohm re-
sistor is recommend between the analog and digital supply
lines, with a ceramic capacitor close to the analog supply pin.
Avoid inductive components in the analog supply line.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the A/D analog supply.
As is the case with all high speed converters, the ADC1173
should be assumed to have little a.c. power supply rejection,
especially when self-biasing is used by connecting V
V
No pin should ever have a voltage on it that is in excess of the
supply voltages or below ground, not even on a transient ba-
sis. This can be a problem upon application of power to a
circuit. Be sure that the supplies to circuits driving the CLK,
OE, analog input and reference pins do not come up any
faster than does the voltage at the ADC1173 power pins.
Pins 11 and 13 are both labeled DV
point for the digital core of the ADC, where pin 13 is used only
to provide power to the ADC output drivers. As such, pin 11
may be connected to a voltage source that is less than the
+5V used for AV
age devices. Pin 11 should never exceed the pin 13 potential
by more than 0.5V. Note that t
voltages.
4.0 THE ADC1173 CLOCK
Although the ADC1173 is tested and its performance is guar-
anteed with a 15MHz clock, it typically will function with clock
frequencies from 1MHz to 20MHz.
If continuous conversions are not required, power consump-
tion can be reduced somewhat by stopping the clock at a logic
low when the ADC1173 is not being used. This reduces the
current drain in the ADC1173's digital circuitry from a typical
value of 2.3mA to about 100µA.
Note that powering up the ADC1173 without the clock running
may not save power, as it will result in an increased current
flow (by as much as 170%) in the reference ladder. In some
RTS
RT
A
RB
RTS
. Best performance can be realized with V
RB
= 0.36V. If V
can be anywhere between V
) should be a minimum of 1.0V and a maximum of about
and V
together.
RBS
pins are left floating.
RB
DD
RT
is not required to be below about +700mV,
and DV
. To minimize noise effects and ensure
RB
can be anywhere between ground
DD
OD
to ease interfacing to low volt-
will increase for lower pin 11
RB
DD
+ 1.0V and the analog
. Pin 11 is the supply
RT
= 1.56 and
RT
and
RT
17
cases, this may increase the ladder current above the speci-
fied limit. Toggling the clock twice at 1MHz or higher and
returning it to the low state will eliminate the excess ladder
current.
An alternative power-saving technique is to power up the
ADC1173 with the clock active, then halt the clock in the low
state after two or more clock cycles. Stopping the clock in the
high state is not recommended as a power-saving technique.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals is essential
to ensure accurate conversion. Separate analog and digital
ground planes that are connected beneath the ADC1173 may
be used, but best EMI practices require a single ground plane.
However, it is important to keep analog signal lines away from
digital signal lines and away from power supply currents. This
latter requirement requires the careful separation and place-
ment of power planes. The use of power traces rather than
one or more power planes is not recommended as higher fre-
quencies are not well filtered with lumped capacitances. To
filter higher frequency noise, it is necessary to have sufficient
capacitance between the power and ground planes.
If separate analog and digital ground planes are used, the
analog and digital grounds should be in the same layer, but
should be separated from each other. If separate analog and
digital ground layers are used, they should never overlap
each other.
Capacitive coupling between a typically noisy digital ground
plane and the sensitive analog circuitry can lead to poor per-
formance that may seem impossible to isolate and remedy.
The solution is to keep the analog circuity well separated from
the digital circuitry.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have signif-
icant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74HC(T) and 74AC(T)Q families.
The worst noise generators are logic families that draw the
largest supply current transients during clock or signal edges,
like the 74F and the 74AC(T) families. In general, slower logic
families, such as 74LS and 74HC(T), will produce less high
frequency noise than do high speed logic families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated nose.
This is because of the skin effect. Total surface area is more
important that is total ground plane volume.
An effective way to control ground noise is by using a single,
solid ground plane, splitting the power plane into analog and
digital areas and to have power and ground planes in adjacent
board layers. There should be no traces within either the
power or the ground layers of the board. The analog and dig-
ital power planes should reside in the same board layer so
that they can not overlap each other. The analog and digital
power planes define the analog and digital areas of the board.
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
In high frequency systems, however, avoid crossing analog
and digital lines altogether. Clock lines should be isolated
from ALL other lines, analog and digital. Even the generally
accepted 90 degree crossing should be avoided as even a
little coupling can cause problems at high frequencies. Best
performance at high frequencies and at high resolution is ob-
tained with a straight signal path.
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