adc10732 National Semiconductor Corporation, adc10732 Datasheet - Page 3

• Manufacturer Part Number: adc10732
• Description: 10-bit Plus Sign Serial I/o A/d Converters With Mux, Sample/hold And Reference
• Manufacturer: National Semiconductor Corporation

Ordering Information
* These products are obsolete or on lifetime buy and shown
for reference only.
Pin Descriptions
CLK
DI
DO
CS
PD
SARS
The clock applied to this input controls the suc-
cessive approximation conversion time interval,
the acquisition time and the rate at which the
serial data exchange occurs. The rising edge
loads the information on the DI pin into the mul-
tiplexer address shift register. This address con-
trols which channel of the analog input multi-
plexer (MUX) is selected. The falling edge shifts
the data resulting from the A/D conversion out on
DO. CS enables or disables the above functions.
The clock frequency applied to this input can be
between 5 kHz and 3 MHz.
This is the serial data input pin. The data applied
to this pin is shifted by CLK into the multiplexer
address register. Tables 1, 2, 3 show the multi-
plexer address assignment.
The data output pin. The A/D conversion result
(DB0-SIGN) are clocked out by the failing edge
of CLK on this pin.
This is the chip select input pin. When a logic low
is applied to this pin, the rising edge of CLK shifts
the data on DI into the address register. This low
also brings DO out of TRI-STATE after a conver-
sion has been completed.
This is the power down input pin. When a logic
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is powered
up.
This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
ADC10731CIWM *
ADC10732CIWM *
ADC10734CIMSA *
ADC10734CIWM *
ADC10738CIWM
Industrial Temperature Range
−40˚C ≤ T
A
≤ +85˚C
3
CH0–CH7 These are the analog inputs of the MUX. A chan-
COM
V
V
AV
DGND
AGND
REF
REF
+
, DV
+
−
+
at all other times.
nel input is selected by the address information
at the DI pin, which is loaded on the rising edge
of CLK into the address register (see Tables 1, 2,
3).
The voltage applied to these inputs should not
exceed AV
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
This pin is another analog input pin. It can be
used as a “pseudo ground” when the analog
multiplexer is single-ended.
This is the positive analog voltage reference in-
put. In order to maintain accuracy, the voltage
range V
5.0 V
AV
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND − 50 mV or exceed AV
+ 50 mV.
These are the analog and digital power supply
pins. These pins should be tied to the same
power supply and bypassed separately. The op-
erating voltage range of AV
to 5.5 V
This is the digital ground pin.
This is the analog ground pin.
Package
MSA20
M16B
M20B
M20B
M24B
+
+50 mV.
DC
REF
DC
and the voltage at V
.
+
(V
or go below GND by more than
REF
= V
REF
+–V
+
REF
and DV
REF
+ cannot exceed
−) is 0.5 V
+
www.national.com
is 4.5 V
DC
DC
to
+