adc1020 austriamicrosystems, adc1020 Datasheet - Page 9

• Manufacturer Part Number: adc1020
• Description: Cmos 10-bit Pipelined A/d Converter
• Manufacturer: austriamicrosystems

Datasheet : ADC1020 – C35
FUNCTIONAL BLOCK DIAGRAM
TIMING DIAGRAM
The sampling rate of the AD1020 is defined by the frequency of the CLK signal. The input signal voltage of the ADC is sampled in the falling edge
of CLK. As the conversion stages operate in a staggered fashion in alternate phases of CLK, the duty-cycle of this signal must be 50%. The results
are latched in the output register on the falling edge of CLK, with a latency of 5 CLK periods. The conversion timing is shown in Diagram 1.
Revision C, 07.09.02
Stage 0
Stage 1
Stage 2
Stage 9
Output
Digital
Cycle
CLK
S/H
Sample of x
In
Clk
0
(1)
x
0
1
Sa mple & Quant.
S/H
Hold of x
Tsd
of
x
x
1
1
(1)
1
Ts
(1)
2b
FLASH
MDAC
D1
D2
D7
D8
1
Sa mple & Quant.
1
Sa mple of x
Amplific ation
of
of x
x
x
Diagram 1: Timing of the pipelining operation
2
2
2
(1)
(1)
0
2b
FLASH
(2)
MDAC
2
D6
D7
2
D1
2
Sa mple & Quant.
Digital Error Correction Logic
Hold of x
Latency of 5 CLKcycles
Amplific ation
of
of
x
x
3
x
1
3
(2)
1
(1)
(2)
2b
FLASH
Sa mple & Quant.
MDAC
Sample of x
D1
D2
Amplification
7
7
of x
of
x
2
2
(7)
x
(7)
8
0
(8)
2b
5
FLASH
MDAC
Sa mple & Quant.
Sample & Quant.
D1
Amplific ation
8
Hold of x
8
of
of
of x
x
x
3
1
(7)
x
9
(8)
(1)
9
1
(8)
2b
FLASH
Sample & Quant.
Sa mple of x
Amplific ation
9
of
of x
x
2
2
(8)
(8)
0
(9)
6
Sa mple & Quant.
Tod
Sa mple & Quant.
Page 9 of 11
10b Out
Amplific ation
Hold of x
of
of
of
q[x(1)]
x
x
x
3
(8)
9
1
(2)
(9)
1
(9)