adc10065cimtx National Semiconductor Corporation, adc10065cimtx Datasheet

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adc10065cimtx

Manufacturer Part Number
adc10065cimtx
Description
10-bit 65 Msps 3v A/d Converter
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2005 National Semiconductor Corporation
ADC10065
10-Bit 65 MSPS 3V A/D Converter
General Description
The ADC10065 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 10-bit
digital words at 65 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize
power consumption, while providing excellent dynamic per-
formance. A unique sample-and-hold stage yields a full-
power bandwidth of 400 MHz. Operating on a single 3.0V
power supply, this device consumes just 68.4 mW at
65 MSPS, including the reference current. The Standby
feature reduces power consumption to just 14 .1 mW.
The differential inputs provide a full scale selectable input
swing of 2.0 V
single-ended input. Full use of the differential input is recom-
mended for optimum performance. An internal +1.2V preci-
sion bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered refer-
enced voltage for those applications requiring increased ac-
curacy. The output data format is 10-bit offset binary, or two’s
complement.
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
Connection Diagram
P-P
, 1.5 V
P-P
, 1.0 V
P-P
, with the possibility of a
DS200779
Features
n Single +3.0V operation
n Selectable 2.0 V
n 400 MHz −3 dB input bandwidth
n Low power consumption
n Standby mode
n On-chip reference and sample-and-hold amplifier
n Offset binary or two’s complement data format
n Separate adjustable output driver supply to
n 28-pin TSSOP package
Key Specifications
n Resolution
n Conversion Rate
n Full Power Bandwidth
n DNL
n SNR (f
n SFDR (f
n Data Latency
n Supply Voltage
n Power Consumption, 65 MHz
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Based Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
swing
accommodate 2.5V and 3.3V logic families
IN
IN
= 11 MHz)
= 11 MHz)
20077901
P-P
, 1.5 V
P-P
, or 1.0 V
P-P
6 Clock Cycles
full-scale input
±
www.national.com
0.3 LSB (typ)
59.6 dB (typ)
−80 dB (typ)
May 2005
65 MSPS
400 MHz
68.4 mW
10 Bits
+3.0V

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adc10065cimtx Summary of contents

Page 1

... The output data format is 10-bit offset binary, or two’s complement. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40˚C to +85˚C. Connection Diagram © 2005 National Semiconductor Corporation Features n Single +3.0V operation n Selectable 2.0 V swing n 400 MHz −3 dB input bandwidth ...

Page 2

... Ordering Information Industrial (−40˚C ≤ T ADC10065CIMTX Block Diagram www.national.com ≤ +85˚C) A ADC10065CIMT 28 Pin TSSOP 28 Pin TSSOP Tape & Reel 2 NS Package 20077902 ...

Page 3

Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I − REF 7 V REFT 4 V COM 8 V REFB DIGITAL I/O 1 CLK STBY IRS (Input ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol 16–20, D0–D9 23–27 ANALOG POWER DDA 3, 11 SSA DIGITAL POWER 22 V DDIO 21 V SSIO www.national.com (Continued) Equivalent Circuit Digital output data ...

Page 5

Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications DDA DDIO Voltage on Any Pin to GND Input Current on Any Pin Package Input ...

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DC and Logic Electrical Characteristics apply for 0V, V SSA SSIO DDA MHz, 50% Duty Cycle, C CLK L Symbol Parameter CLK, DF, STBY, SENSE Logical “1” Input Voltage Logical “0” Input Voltage ...

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AC Electrical Characteristics Unless otherwise specified, the following specifications apply for STBY = 0V 1.20V, (Externally Supplied) f P-P REF ply for all other limits T A MIN ...

Page 8

Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

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Timing Diagram Transfer Characteristics FIGURE 2. Input vs. Output Transfer Characteristic FIGURE 1. Clock and Data Timing Diagram 9 20077909 20077910 www.national.com ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA MHz, 50% Duty Cycle. IN DNL DNL vs. Clock Duty Cycle (DC input) INL www.national.com Unless otherwise specified, the following specifications apply: ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA DDIO MHz, 50% Duty Cycle. (Continued) IN INL vs. Clock Duty Cycle SNR vs. V DDA INL vs. Temperature Unless otherwise specified, ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA MHz, 50% Duty Cycle. (Continued) IN SNR vs. Temperature THD vs. V DDIO SNR vs. IRS www.national.com Unless otherwise specified, the following ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA DDIO MHz, 50% Duty Cycle. (Continued) IN SINAD vs. V DDA THD vs. Clock Duty Cycle THD vs. Temperature Unless otherwise specified, ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA MHz, 50% Duty Cycle. (Continued) IN SINAD vs. f CLK SINAD vs. IRS SFDR vs. V DDA www.national.com Unless otherwise specified, the ...

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Typical Performance Characteristics 0V +3.0V, V SSA SSIO DDA DDIO MHz, 50% Duty Cycle. (Continued) IN SFDR vs. Clock Duty Cycle SFDR vs. Temperature Power Consumption vs. f Unless otherwise specified, ...

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Functional Description The ADC10065 uses a pipeline architecture and has error correction circuitry to help ensure maximum performance. Differential analog input signals are digitized to 10 bits. In differential mode, each analog input signal should have a peak-to-peak voltage equal ...

Page 17

Applications Information TABLE 1. IRS Pin Functions IRS Pin Full-Scale Input V 2.0V DDA V 1.5V SSA Floating 1.0V 1.8 OUTPUT PINS The ADC10065 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these outputs ...

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Applications Information FIGURE 6. A Simple Application Using a Single Ended Driving Source www.national.com (Continued) 18 20077950 ...

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Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and ...

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