adc12c170lfeb National Semiconductor Corporation, adc12c170lfeb Datasheet - Page 20

• Manufacturer Part Number: adc12c170lfeb
• Description: 12-bit, 170 Msps, 1.1 Ghz Bandwidth A/d Converter With Cmos Outputs
• Manufacturer: National Semiconductor Corporation

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short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90° crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because oth-
er lines can introduce jitter into the clock line, which can lead
to degradation of SNR. Also, the high speed clock can intro-
duce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors and trans-
formers. Mutual inductance can change the characteristics of
the circuit in which they are used. Inductors and transformers
should not be placed side by side, even with just a small part
of their bodies beside each other. For instance, place trans-
formers for the analog input and the clock input at 90° to one
another to avoid magnetic coupling.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
All analog circuitry (input amplifiers, filters, reference compo-
nents, etc.) should be placed in the analog area of the board.
All digital circuitry and dynamic I/O lines should be placed in
the digital area of the board. The ADC12C170 should be be-
tween these two areas. Furthermore, all components in the
reference circuitry and the input signal chain that are con-
nected to ground should be connected together with short
traces and enter the ground plane at a single, quiet point. All
ground connections should have a low inductance path to
ground.
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7.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must have a sharp transition region and
be free of jitter. Isolate the ADC clock from any digital circuitry
with buffers, as with the clock tree shown in Figure 5 . The
gates used in the clock tree must be capable of operating at
frequencies much higher than those used if added jitter is to
be prevented. Best performance will be obtained with a sin-
gle-ended drive input drive, compared with a differential clock.
As mentioned in Section 6.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90° crossings have capacitive coupling, so try
to avoid even these 90° crossings of the clock line.
FIGURE 5. Isolating the ADC Clock from other Circuitry
with a Clock Tree
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