adc12d040civsx National Semiconductor Corporation, adc12d040civsx Datasheet - Page 17

• Manufacturer Part Number: adc12d040civsx
• Description: Dual 12-bit, 40 Msps, 600 Mw A/d Converter With Internal/external Reference And Sample-and-hold
• Manufacturer: National Semiconductor Corporation

Applications Information
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
such that the peak excursions of the analog signal does not
go more negative than ground or more positive than 1.0
Volts below the V
generally be about V
V
pins.
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, OEA,
OEB, OF, INT/EXT REF, and PD.
CM
sources as long as no d.c. current is drawn from these
A
FIGURE 4. Application Circuit using Transformer or Differential Op-Amp Drive Circuit
supply voltage. The nominal V
REF
/2. V
FIGURE 5. Differential Drive Circuit using a fully differential amplifier.
RB
A and V
CM
, should be of a value
RB
B can be used as
(Continued)
CM
should
17
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 55 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample
20046014
www.national.com
20046013