adc08d1010diyb National Semiconductor Corporation, adc08d1010diyb Datasheet - Page 6

• Manufacturer Part Number: adc08d1010diyb
• Description: High Performance, Low Power, Dual 8-bit, 1 Gsps A/d Converter
• Manufacturer: National Semiconductor Corporation

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Pin Functions
100 / 61
101 / 60
102 / 59
103 / 58
104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
124 / 37
125 / 36
Pin No.
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
32
34
35
79
80
82
81
DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
Tdiode_P
Tdiode_N
Symbol
DCLK+
DCLK-
R
OR+
OR-
EXT
Equivalent Circuit
6
External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
Temperature Diode Positive (Anode) and Negative (Cathode) for
die temperature measurements. See Section 2.6.2.
I and Q channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the DId and DQd outputs,
these outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the DI/DQ
outputs, these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω differential
resistor.
Out Of Range output. A differential high at these pins indicates that
the differential input is out of range (outside the range as defined
by the FSR pin).
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode and
at 1/4 the input clock rate in the DDR mode.
Description