adc0800pd National Semiconductor Corporation, adc0800pd Datasheet - Page 3

• Manufacturer Part Number: adc0800pd
• Description: 8-bit A/d Converter
• Manufacturer: National Semiconductor Corporation

Timing Diagram
Application Hints
OPERATION
The ADC0800 contains a network with 256-300X resistors
in series Analog switch taps are made at the junction of
each resistor and at each end of the network In operation
a reference (10 00V) is applied across this network of 256
resistors An analog input (V
ter point of the ladder via the appropriate switch If V
larger than V
points and now compares V
known as successive approximation continues until the
best match of V
specific tap on the resistor network When the conversion is
complete the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears The output latches hold this data
valid until a new conversion is completed and new data is
loaded into the latches The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches The data outputs are activated when the Output
Enable is high and in TRI-STATE when Output Enable is
low The Enable Delay time is approximately 200 ns Each
conversion requires 40 clock periods The device may be
operated in the free running mode by connecting the Start
Conversion line to the End of Conversion line However to
ensure start-up under all possible conditions an external
Start Conversion pulse is required during power up condi-
tions
REFERENCE
The reference applied across the 256 resistor network de-
termines the analog input range V
of the R-network connected to 5V and the bottom connect-
ed to
shifted between V
plied to the top of the R-network (pin 15) must not exceed
V
diodes that exist between the P-diffused resistors (pin 15)
and the N-type body (pin 10 V
power supply for V
voltage tolerance and changes over temperature A solution
is to power the V
of the op amp that is used to bias the top of the
SS
to prevent forward biasing the on-chip parasitic silicon
b
5V gives a
REF
IN
SS
2 the internal logic changes the switch
SS
SS
and V
g
line (15 mA max drain) from the output
can cause problems both due to initial
5V range The reference can be level
and V
REF
IN
GG
IN
) is first compared to the cen-
N is made N now defines a
SS
and
However the voltage ap-
) Use of a standard logic
REF
e
V
10 00V with the top
Data is complementary binary (full scale is all ‘‘0’s’’ output)
REF
This process
IN
is
3
R-network (pin 15) The analog input voltage and the volt-
age that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the
ensure adequate voltage drive to the analog switches
Other reference voltages may be used (such as 10 24V) If a
5V reference is used the analog range will be 5V and accu-
racy will be reduced by a factor of 2 Thus for maximum
accuracy it is desirable to operate with at least a 10V refer-
ence For TTL logic levels this requires 5V and
R-network CMOS can operate at the 10 V
a single 10 V
levels for both inputs and outputs will be from ground to
V
ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS
The lead to the analog input (pin 12) should be kept as short
as possible Both noise and digital clock coupling to this
input can cause conversion errors To minimize any input
errors
should be noted
For R
For 5k
For R
If the overall converter system requires lowpass filtering of
the analog input signal use a 20 kX or less series resistor
for a passive RC section or add an op amp RC active low-
pass filter (with its inherent low output resistance) to ensure
accurate conversions
CLOCK COUPLING
The clock lead should be kept away from the analog input
line to reduce coupling
LOGIC INPUTS
The logical ‘‘1’’ input voltage swing for the Clock Start Con-
version and Output Enable should be (V
SS
S s
S l
k
the following source resistance considerations
R
5k
20k
S s
20k
DC
reference can be used All digital voltage
No analog input bypass capacitor re-
quired although a 0 1 mF input bypass
capacitor will prevent pickup due to un-
avoidable series lead inductance
A 0 1 mF capacitor from the input (pin
12) to ground should be used
Input buffering is necessary
b
V
GG
SS
supply voltage to
DC
b
1 0V)
V
SS
b
TL H 5670 – 2
5V for the
level and