max5774 Maxim Integrated Products, Inc., max5774 Datasheet - Page 19

• Manufacturer Part Number: max5774
• Description: 32-channel, 14-bit, Voltage-output Dacs With Serial Interface
• Manufacturer: Maxim Integrated Products, Inc.

word to control the device. The command word consists
of 4 control bits, 6 address bits, 14 data bits (and S1, S0
= 00), and 6 don’t-care bits.
serial data format. The control bits control various write
and read commands, as well as the load DAC and MAC-
bypass commands.
tions. The address bits select the register(s) to update.
Figure
trol the voltage value of the DAC outputs. DIN data is
clocked in at the falling edge of SCLK
The MAX5773/MAX5774/MAX5775 contain a gain and
offset register associated with each channel to correct
Table 8. Control-Bit Functions
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4 CONTROL BITS
3 shows the address functions. The data bits con-
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
______________________________________________________________________________________
Table
Gain and Offset Registers
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8 shows the control-bit func-
Table
No operation (NOP). No internal registers change state. The NOP command can be passed to
DOUT depending on the state of the configuration register. Address bits A5–A0 and data bits
D13–D0 are ignored.
This instruction writes and calibrates the 14-bit input data word for gain and offset errors. Drive
LDAC low or use a software load-DAC command to update the selected DAC outputs.
Software load-DAC command. Updates the output of the selected DAC channel(s). Depending on
the address bits, this command updates one DAC output, a pair of DAC outputs, or all the DAC
outputs simultaneously. Data bits D13–D0 are ignored.
This instruction writes and calibrates the 14-bit input data word for gain and offset errors and
immediately updates the DAC outputs for the selected address.
Read command. Depending on the address bits, one of the input register values is read back
through DOUT. Data bits D13–D0 are ignored. See the Daisy-Chain Operation section.
Reserved; do not use.
Reserved; do not use.
MAC-bypass command. Depending on the address bits, one, two, or all DAC registers are loaded
with a 14-bit data word at DIN. The input data is not calibrated for gain and offset errors (see the
MAC-Bypass section). Selected DAC output(s) are immediately updated.
Loads D13–D0 into one or two of the gain register(s) for the selected address. The data for the
selected address is calibrated for gain error. Drive LDAC low or use a software load-DAC
command to update the selected DAC outputs.
Loads D13–D0 into one or two of the offset register(s) for the selected address. The data for the
selected address is calibrated for offset error. Drive LDAC low or use a software load-DAC
command to update the selected DAC outputs.
Read command. Reads one of the gain registers and presents the data at DOUT.
Read command. Reads one of the offset registers and presents the data at DOUT.
Write command. Loads D13–D0 into the configuration register.
Read command. Reads the contents of the configuration register.
Read command. Reads the DAC register for the selected address.
Reset instruction.
32-Channel, 14-Bit, Voltage-Output
6 shows the general
(Figure
1).
DACs with Serial Interface
CONTROL-BIT DESCRIPTION
Table 7. Gain and Offset Register Input
Data Format
*S1 = S0 = 0 for proper 14-bit operation.
R E G I ST ER
Register
Register
Offset
Gain
C O N T R O L
( C 3 – C 0 )
B IT S
1001
1000
S ee Fi g ur e 3
S ee Fi g ur e 3
ADDRESS
(A5–A0)
BITS
D A T A B I T S
( D 1 3 – D 0
A N D S1 , S0 * )
S ee Tab l e 9
S ee Tab l e
10
X X X X X X
X X X X X X
DON’T-
CARE
BITS
6
19