max5873egktd Maxim Integrated Products, Inc., max5873egktd Datasheet - Page 10

• Manufacturer Part Number: max5873egktd
• Description: Max5873 12-bit, 200msps, High-dynamic-performance, Dual Dac With Cmos Inputs
• Manufacturer: Maxim Integrated Products, Inc.

12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
Figure 1. MAX5873 High-Performance, 12-Bit, Dual Current-Steering DAC
Each MAX5873 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25Ω termination resistor to ground and a
50Ω resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5873.
The MAX5873 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
10
______________________________________________________________________________________
DATA11–
DATA0
(OUTIP, OUTIN, OUTQP, OUTQN)
SELIQ
AV
TORB
CLKP
CLKN
DORI
GND
XOR
CLK
Clock Inputs (CLKP, CLKN)
RECEIVER
DV
CMOS
DD3.3
GND
LATCH
Analog Outputs
INTERFACE
POWER-DOWN
CLK
BLOCK
DV
PD
DD1.8
LATCH
LATCH
AV
DD1.8
MAX5873
DECODE
DECODE
(AV
mance. Drive the differential clock inputs from a single-
ended or a differential clock source. For single-ended
operation, drive CLKP with a logic source and bypass
CLKN to GND with a 0.1µF capacitor.
CLKP and CLKN are internally biased to AV
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is > 5kΩ.
Figure 4 displays the timing relationship between digital
CMOS data, clock, and output signals. The MAX5873
features a 1.5ns hold, a -1.2ns setup, and a 1.1ns prop-
agation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN, and OUTIP/OUTIN
(OUTQP/OUTQN) when operating in single-port (inter-
leaved) mode. In dual-port (parallel) mode, the clock
latency is 5.5 clock cycles for both channels.
XOR/
XOR/
CLK
) to achieve the lowest possible jitter perfor-
LATCH
LATCH
GND
AV
DD3.3
Data Timing Relationship
LATCH
LATCH
REFERENCE
1.2V
DAC
DAC
DACREF
OUTQP
OUTQN
FSADJ
OUTIP
OUTIN
REFIO
CLK
/ 2. This