max5852etlt Maxim Integrated Products, Inc., max5852etlt Datasheet - Page 12

• Manufacturer Part Number: max5852etlt
• Description: Max5852 Dual, 8-bit, 165msps, Current-output Dac
• Manufacturer: Maxim Integrated Products, Inc.

Dual, 8-Bit, 165Msps, Current-Output DAC
Table 1. Control Word Format and Function
Table 2. Configuration Modes
X = Don’t care.
Table 3. Gain Difference Setting
12
Normal operation;
noninterleaved inputs;
internal reference active
Normal operation;
noninterleaved inputs;
internal reference disabled
Normal operation;
interleaved inputs; internal
reference disabled
Standby
Power-down
Power-up
CONTROL WORD
MSB
GAIN ADJUSTMENT ON
______________________________________________________________________________________
PD
DACEN
CHANNEL A (dB)
REN
IDE
PD
G3
G2
G1
G0
MODE
-0.35
+0.4
0
DACEN
Power-Down. The part enters power-down mode if PD = 1.
DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.
Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.
Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.
Bit 3 (MSB) of Gain Adjust Word
Bit 2 of Gain Adjust Word
Bit 1 of Gain Adjust Word
Bit 0 (LSB) of Gain Adjust Word
PD
0
0
0
0
1
0
G3
0
1
1
DACEN
IDE
1
1
1
0
X
1
G2
0
0
1
IDE
0
0
1
X
X
X
G1
0
0
1
REN
REN
0
1
1
X
X
X
G0
0
0
1
At power-up, the MAX5852’s default configuration is
internal reference, noninterleaved input mode with a gain
of 0dB and a fully operational converter. In shutdown,
the MAX5852 consumes only 1µA of supply current, and
in standby the current consumption is 3.1mA. Wake-up
time from standby mode to normal operation is 3µs.
The MAX5852 allows both single-ended CMOS and dif-
ferential clock mode operation, and supports update
rates of up to 165Msps. These modes are selected
through an active-low control line called DCE. In single-
ended clock mode (DCE = 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.
If the DCE pin is pulled low, the MAX5852 will operate in
differential clock mode. In this mode, the clock signal has
to be applied to differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
range of ≥0.5V
(CV
tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscillator
directly to MAX5852.
FUNCTION
DD
G3
- 0.5V), making the part ideal for low- input ampli-
P-P
G2
and a common-mode range of 1V to
Device Power-Up and
States of Operation
G1
Clock Modes
G0
LSB