max5888egktd Maxim Integrated Products, Inc., max5888egktd Datasheet - Page 10
max5888egktd
Manufacturer Part Number
max5888egktd
Description
Max5888 3.3v, 16-bit, 500msps High Dynamic Performance Dac With Differential Lvds Inputs
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.MAX5888EGKTD.pdf
(18 pages)
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5888.
The MAX5888 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the lowest possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For sin-
gle-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to 1.5V.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5kΩ.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from an
LVDS-compatible clock source; however, it is recom-
mended to use sinewave or AC-coupled ECL drive for
best performance.
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
Figure 2. Reference Architecture, Internal Reference
Configuration
10
I
REF
I
REF
= V
______________________________________________________________________________________
REFIO
0.1µF
R
DACREF
/R
SET
FSADJ
REFIO
SET
REFERENCE
10kΩ
1.2V
Clock Inputs (CLKP, CLKN)
CURRENT-STEERING
DAC
AV
DD
IOUTP
IOUTN
Figure 5 shows the timing relationship between differ-
ential, digital LVDS data, clock, and output signals. The
MAX5888 features a 1.4ns hold, a -1ns setup, and a
1.8ns propagation delay time. There is a 3.5 clock-
cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
The MAX5888 features LVDS receivers on the bus input
interface. These LVDS inputs (B0P/N through B15P/N)
allow for a low-differential voltage swing with low con-
stant power consumption across a large range of
Figure 3. Simplified Analog Output Structure
Figure 4. Differential Clock Signal Generation
SWITCHES
CURRENT
CLOCK SOURCE
(e.g., HP 8662A)
SINGLE-ENDED
AV
DD
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
LVDS-Compatible Digital Inputs
CURRENT
SOURCES
1:1
Data Timing Relationship
CLKGND
(B0P–B15P, B0N–B15N)
25Ω
25Ω
0.1µF
0.1µF
I
OUT
IOUTN
CLKN
CLKP
DAC
TO
IOUTP
I
OUT