max5079eudt Maxim Integrated Products, Inc., max5079eudt Datasheet - Page 13

• Manufacturer Part Number: max5079eudt
• Description: Max5079 Oring Mosfet Controller With Ultra-fast 200ns Turn-off
• Manufacturer: Maxim Integrated Products, Inc.

V
above V
V
while higher gatedrive means lower R
A fast and slow comparator monitor the voltage from IN
to BUS. When this voltage crosses the negative fast- or
slow-comparator threshold voltage for the blanking time
duration, GATE is pulled low by an internal 2A current
sink. Both comparators have an adjustable threshold
voltage. GATE is pulled low if any of the following con-
ditions are met.
1) V
2) V
3) V
4) V
When the above conditions are not true and V
V
MOSFET is quickly turned off, given the above condi-
tions, the GATE pulldown circuitry is powered by either
V
then 2.75V.
The fast comparator has a 50ns blanking time to avoid
unintentional turn-off of the ORing MOSFET during fast
transients. Additionally, the fast-comparator reverse
voltage threshold (V
need of an individual application. Higher V
old allows for a larger glitch at BUS during a fault, but
improves the noise immunity. Lower V
glitches at BUS during a fault, however, with lower V
spikes at BUS or glitches at IN can be read as faults,
unintentionally turning off the ORing MOSFET. Program
V
V
lowing equation:
V
FTH to GND to choose the default 24mV threshold.
IN
IN
BUS
FTH
FTH
IN
FTH
(V
. Lower gate drive means faster turn-off during faults,
, V
= 5V or V
UVLO
AUXIN
OVI
IN
GATE
, GATE is shorted to IN. To insure that the external
by connecting a resistor from FTH to GND. Adjust
to optimize the system performance using the fol-
can be chosen from 24mV to 400mV. Connect
AUXIN
≤ (V
≥ 0.6V.
IN
< 0.6V.
< 2.25V and V
- V
and for V
BUS
, or V
IN
IN
) ≥ 1.8V.
= 12V. For V
- V
R
______________________________________________________________________________________
BUS
FTH
FTH
IN
FTH
> 8V, the gate drive is 7V above
=
as long as any one is greater
) or V
) is programmable to suit the
IN
V
FTH
< 2.25V.
6 67
IN
.
IN
−
≤ 8V, the gate drive is 5V
Fast Comparator (FTH)
24
µ
≤ (V
A
mV
DSON
BUS
ORing MOSFET Controller with
.
FTH
- V
FTH
STH
reduces
thresh-
) and
IN
FTH
≤
Ultra-Fast 200ns Turn-Off
The MAX5079 includes a slow comparator to provide
glitch immunity during the hot insertion or removal of
paralleled power supplies. During the hot insertion,
BUS can see voltage spikes. These spikes can be
interpreted as a reverse voltage across the ORing
MOSFET. The amplitude of the spikes is proportional to
the load step seen by the parallel power supply while
the duration of the spikes depends on the loop
response of the load share and PWM controller.
The slow comparator has a programmable reverse volt-
age threshold (V
ing time (t
converts the IN to BUS differential voltage to a current
and applies it to a parallel combination of resistor and
capacitor (R
reverse threshold voltage (V
tor is adjusted through R
tion to calculate the R
where G
The internal 500kΩ resistance from the output of the
transconductance to GND can change the actual V
if R
Operating Circuit to select R
the blanking time can be adjusted by C
time is:
where t
generated by an internal digital delay. Leaving STH
floating results in a 12mV threshold voltage and a 0.9ms
blanking time. V
actual reverse voltage (V
OVI is the negative input to the overvoltage compara-
tor. The positive input of this comparator is connected
to the internal 0.6V reference and an open-drain output
is provided at OVP. The overvoltage sensing for over-
voltage protection is done at either IN or BUS. OVP
t
DELAY
STH
Overvoltage Protection Latch (OVI/OVP)
SBL
is above 50kΩ. In this case, see the Typical
M_STH
=
R
STH
R
STH
STH
= 0.9ms and is the default blanking time
STH
). An internal transconductance amplifier
= 0.17mS.
OD
=
×
STH
C
(
and C
V
STH
(overdrive) is the difference between
STH
) as well as a programmable blank-
STH
× −
−
BUS
STH
12




STH
for a required V
mV x G
ln 1
STH
STH
- V
) from STH to GND. The
1
. Use the following equa-



V
Slow Comparator (STH)
)
IN
−
) for the slow compara-
. Once R
) and V
V
STH
M STH
V
STH
_
+
STH
STH
V
STH
STH
DD
. The delay
threshold.
.



is chosen,




+
t
SBL
STH
13