ad8381 Analog Devices, Inc., ad8381 Datasheet
ad8381
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ad8381 Summary of contents
Page 1
... The AD8381 dissipates 570 mW nominal static power. The STBY pin reduces power to a minimum, with fast recovery. The AD8381 is offered in a 48-lead 7 mm ¥ ¥ 1.4 mm LQFP package and operates over the commercial temperature range of 0∞C to 85∞C. ...
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... AD8381–SPECIFICATIONS Model 1 VIDEO DC PERFORMANCE VDE VCME REFERENCE INPUTS 2 VMID Range VMID Bias Current VREFHI VREFLO VREFHI Input Resistance VREFLO Bias Current VREFHI Input Current 3 VFS Range RESOLUTION Coding DIGITAL INPUT CHARACTERISTICS Input Data Update Rate CLK to Data Setup Time CLK to STSQ Setup Time: t ...
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... CLK Rise and Fall Time = 5 ns – Figure 1. Timing Requirement E/O = High – Figure 2. Timing Requirements E/O = Low t 7 Figure 3. Output Timing –3– Min Typ Max 13.5 15.5 17 AD8381 Unit ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8381 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... CLK and the E/O input is held low. Data is transferred to the outputs on the immediately following falling edge of CLK when this input is high on the rising edge of CLK. Clock Input. –5– AD8381 36 VID0 AVCC0 VID1 ...
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... Performance Characteristics AD8381 12V 2V TPC 1. Invert Switching 10 V Step Response (Rise TPC 2. Data Switching 5 V Step Response (Rise INV = L L 12V 7V TPC 3. Data Switching 5 V Step Response (Rise INV = H L 12V VMID = 7V VFS = 5V VIDx C L 150pF ...
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... L 150pF –0.50% –0.75% 10ns/DIV , TPC 11. Output Settling Time (Falling Edge Step, INV = High +10mV VMID = 7V –10mV 20ns/DIV TPC 12. Data Switching Transient (Feedthrough –7– AD8381 2V VMID = 7V VFS = 5V VIDx 10ns/DIV VMID = 7V VFS = 5V VIDx 10ns/DIV DB (0:9) 20ns/DIV C L 150pF ...
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... AD8381 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 256 512 INPUT CODE TPC 13. Differential Nonlinearity (DNL) vs. Code, INV = H 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 256 512 INPUT CODE TPC 14. Integral Nonlinearity (INL) vs. Code, INV = –5 –10 –15 –20 – VMID – V TPC 15 ...
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... TPC 20. Differential Error Voltage (VDE) vs. Temperature REV. B 3.50 1.75 0.00 –1.75 –3.50 0 768 1023 TPC 21. Common-Mode Error Voltage (VCME) vs. Code 3.50 1.75 0.00 –1.75 –3. 100 TPC 22. Common-Mode Error (VCME) vs. Temperature –9– AD8381 256 512 768 1023 INPUT CODE CODE 512 100 TEMPERATURE – C ...
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... AD8381 FUNCTIONAL DESCRIPTION The AD8381 is a system building block designed to directly drive the columns of LCD panels of the type popularized for use in data projectors. It comprises six channels of precision 10-bit digital-to-analog converters loaded from a single, high speed, 10-bit-wide input. Precision current feedback amplifiers, provid- ing well-damped pulse response and rapid voltage settling into large capacitive loads, buffer the six outputs ...
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... TRANSFER FUNCTION The AD8381 has two regions of operation, selected by the INV input, where the video output voltages are either above or below a reference voltage, applied externally at the VMID input. The transfer function defines the analog output voltage as the function of the digital input code as follows: = ± ...
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... LCD per color. The maximum resolution of such a system is usually XGA SXGA and requires two AD8381s per color. One AD8381 is set to run in even mode while the other is in odd mode. Both AD8381s share the same data bus and CLK. The timing diagram of such system is shown in Figure 8. ...
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... CH 0 VID0 CLK XFR VID1 CH 2 R/L VID2 CH 4 STSQ INV VID3 VID4 VREFHI VID5 CH 10 VMID VREFLO 12-CHANNEL LCD DB(0:9) AD8381 CH 1 VID0 CLK VID1 CH 3 XFR R/L VID2 CH 5 STSQ VID3 CH 7 INV E/O VID4 CH 9 VREFHI VID5 CH 11 VMID VREFLO ...
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... Note that digital signals should not cross or be routed near analog signals imperative to provide a solid analog ground plane under and around the AD8381. All of the ground pins of the part should be connected directly to the ground plane with no extra signal path length. For conventional operation this includes the pins DGND, AGNDDAC, AGNDBIAS, AGND0, AGND1,2, AGND3,4, and AGND5 ...
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... REV. B OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0. SEATING 10 PLANE 6 0.20 2 0.09 VIEW 0.08 MAX 0.50 COPLANARITY BSC VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC –15– AD8381 9.00 BSC PIN 1 7.00 TOP VIEW BSC SQ (PINS DOWN 0.27 0.22 0.17 ...
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... AD8381 Revision History Location 10/03—Change from REV REV. B. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9/03—Change from REV REV. A. Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 –16– Page REV. B ...