ml2036 Microsemi Corporation, ml2036 Datasheet - Page 8

• Manufacturer Part Number: ml2036
• Description: Serial Input Programmable Sine Wave Generator With Digital Gain Control
• Manufacturer: Microsemi Corporation

ML2036
FUNCTIONAL DESCRIPTION
The crystal must have the following characteristics:
1. Parallel resonant type
2. Frequency: 3MHz to 12.4MHz
3. Maximum equivalent series resistance of 15
4. Typical load capacitance: 18pF
5. Maximum case capacitance: 7pF
The frequency of oscillation will be a function of the
crystal parameters and PC board capacitance. Crystals that
meet these requirements at 12.352000MHz are M-tron
3709-010 12.352 for 0ºC to 70ºC and 3709-020 12.352
for -40ºC to 85ºC operation.
The ML2036 has two clock outputs that can be used to
drive other external devices. The CLK OUT 1 output is a
buffered output from the oscillator divided by 2. The
CLK OUT 2 output is a buffered output from the oscillator
divided by 8.
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on SID is clocked into a
16-bit shift register on rising edges of the serial shift clock,
SCK. The LSB should be shifted in first and the MSB last as
shown in Figure 4. The data that has been shifted into the
shift register is loaded into a 16-bit data latch on the falling
edge of LATI. To insure that true data is loaded into the
data latch from the shift register, LATI falling edge should
occur when SCK is low, as shown in figure 1. LATI should
be low while shifting data into the shift register to avoid
inadvertently entering the power down mode. Note that all
data is entered and latched on the edges, not levels, of
SCK and LATI.
8
drive levels of 1µW to 200µW, and 30
of 10nW to 1µW
(Continued)
at drive levels
at a
INHIBIT AND POWER DOWN MODES
The ML2036 has an inhibit mode and a power down
mode which are controlled by the three-level P
input as described in Table 1. If a logic "1", (V
to the P
entering all zeros in the shift register and applying a logic
"1" to LATI and holding it high. A zero data detect circuit
detects when all bits in the shift register are zeros. In this
state, the power consumption is reduced to 11.5mW max,
and V
10k to AGND. CLK IN can be left active or removed
during power down mode. Also, the ML2036 can be
placed in the power down mode by applying a logic “0”
to the P
register and the state of LATI.
If V
the inhibit mode is entered by shifting all zeros into the
shift register and applying a logic “1” to the LATI pin.
Once the inhibit mode is entered V
last half cycle of the sinewave and then be held at
approximately V
shown in Figure 6.
POWER SUPPLIES
The analog circuits in ML2036 are powered from V
V
device are powered from V
recommended that AGND and DGND be connected
together close to the device, and have a good connection
back to the power source.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors from
V
device as possible.
SS
CC
SS
and are referenced to AGND. The digital circuits in the
to AGND and V
OUT
to V
DN
DN
SS
–INH pin, the power down mode is entered by
goes to 0V as shown in Figure 6 and appears as
–INH pin, regardless of the contents of the shift
+ 0.5V (V
OS
, such that no voltage step occurs, as
SS
I2
to AGND as physically close to the
) is applied to the P
CC
to DGND. It is
OUT
will complete the
DN
I3
–INH pin,
) is applied
DN
–INH
CC
to