hsp48908 Intersil Corporation, hsp48908 Datasheet - Page 11

• Manufacturer Part Number: hsp48908
• Description: Two Dimensional Convolver
• Manufacturer: Intersil Corporation

is being read synchronous to the internal clock. Therefore,
care must be taken when modifying the convolver setup
parameters during processing to avoid changing the
contents of the registers near a rising edge of CLK. The
required setup time relative to CLK is given by the
Specification TLCS. For example, in order to change the
active Coefficient Register from CREG0 to CREG1 during an
active convolution operation, a write will be performed to the
address for selecting CREG1 for internal processing (A2 -0 =
110). In order to provide proper uninterrupted operation, LD
should be deasserted at least TLCS prior to the next rising
edge of CLK. Failure to meet this setup time may result in
unpredictable results on the output of the convolver for one
clock cycle. Keep in mind that this requirement applies only
to the case where changes are being made in the control
logic during an active convolution operation. In a typical
convolver configuration routine, this specification would not
be applicable.
Cascade I/O
Cascade Input
The cascade input lines (CASl0-15) have two primary
functions. The first is used to allow convolutions with kernel
sizes larger than 3 x 3. This can be implemented by
connecting the DOUT bus of one convolver to the cascade
inputs of another. The second function is for convolution on
images wider than 1024 pixels. This type of operation can be
implemented by using external row buffers to supply the
pixel input data to the CASl0-15 inputs. The cascade input
functions are determined by Initialization Register bit 0.
When this bit is set to a “0”, the cascade input data is added
to the convolver output. In this manner, multiple convolvers
can be used to implement larger kernel convolution. When
Initialization Register bit 0 is “1”, the data on CASl0-15 is
divided into two 8-bit portions and is sent to the 3 x 3
multiplier array (refer to Block Diagram). This mode of
operation allows the use of external row buffers for
convolution of images with row sizes larger than 1024.
Examples of these configurations are given in the
Operations Section of this specification.
A2-0
000
001
010
011
100
101
110
111
Load Row Length Register (RLR).
Load ALU Microcode Register (AMC).
Load Coefficient Register 0 (CREG0).
Load Coefficient Register 1 (CREG1).
Load Initialization Register (INT).
Select CREG0 for Internal Processing.
Select CREG1 for Internal Processing.
No Operation.
CONTROL LOGIC ADDRESS MAP
TABLE 4. ADDRESS MAP
11
FUNCTION
HSP48908
The data on the cascade inputs (CASl0-15) can also be left
shifted by 0, 2, 4, or 8 bits. The amount of shift is determined
by bits 7 and 8 of the Initialization Register (See Table 3).
CASl0-15 is shifted by the specified number of bits and is
added to the 20-bit output DOUT 0-19. The shifting function
provides a method for cascading multiple HSP48908s and
allowing a selectable amount of output growth while
maximizing the resolution of the convolver result.
The cascade inputs can also be used as a simple way to add
an offset to the convolved image. Bit 0 of the Configuration
Register would be set to ‘0’, and the desired offset placed on
the CASl0-15 inputs. While multiple offsets can be used and
changed during the convolution operation, note that the
required data setup and hold times with respect to CLK
(TDS and TDH) must be met.
Cascade Output
The cascade output lines (CASO0-7) are outputs from the
second row buffer. Data at these outputs is the input pixel
data delayed by two times the preprogrammed value in the
Row Length Register. The cascade outputs are used to
cascade multiple convolvers by connecting the cascade
outputs of one device to the data inputs of another (see
Operation Section).
Control Signals
HOLD
The HOLD control input provides the ability to disable
internal clock and stop all operations temporarily. HOLD is
sampled on the rising edge of CLK and takes effect during
the following clock cycle (refer to Figure 2). This signal can
be used to momentarily ignore data at the input of the
convolver while maintaining its current output data and
operational state.
RESET
The RESET signal initializes all internal flip flops and
registers in the HSP48908. It is an asynchronous signal, and
the convolver will remain in the reset state as long as
RESET is asserted. On reset, all internal registers are set to
zero or their default values, and all outputs are forced low.
Following a reset, the default values in the internal registers
will define the following mode of operation: internal row
buffers used, line length = 1024, no input data delay, logical
INTERNAL
CLOCK
HOLD
CLK
FIGURE 2. HOLD OPERATION