hsp45116a Intersil Corporation, hsp45116a Datasheet
hsp45116a
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hsp45116a Summary of contents
Page 1
... As shown in the Block Diagram, the HSP45116A is divided into three main sections. The Phase/ Frequency Control Section (PFCS) and the Sine/Cosine Section together form a complex NCO. The CMAC multiplies the output of the Sine/ Cosine Section with an external complex vector ...
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... Block Diagram MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS 2 HSP45116A SINE/ COSINE PHASE/ ARGUMENT SINE/ FREQUENCY COSINE CONTROL SECTION SECTION VECTOR INPUT R I SIN CMAC COS R I VECTOR OUTPUT May 7, 2007 FN4156.4 ...
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... PEAK 29 RBYTILD 30 BINFMT 31 GND 32 TICO MOD1 35 MOD0 36 PACI 37 LOAD 38 PMSEL HSP45116A HSP45116A (160 LD MQFP) TOP VIEW NC 120 GND 119 IO6 118 IO5 117 IO4 116 IO3 115 GND 114 IO2 113 IO1 112 V 111 CC IO0 110 RO19 ...
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... MODPI/2PI 46 CLROFR 41 LOAD 38 MOD0-1 35 HSP45116A - +5V Power supply input. - Power supply ground input. I Control input bus for loading phase and frequency data into the PFCS. C15 is the MSB. I Address pins for selecting destination of C0-15 data. AD1 is the MSB. I Chip select (active low). ...
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... PEAK 29 5 HSP45116A I Phase Modulation Select Line. This line determines the source of the data clocked into the Phase Register. When high, the Phase Control Register is selected. When low, the external modulation pins (MOD0-1) are selected for the most significant two bits and the least significant two bits and the least significant 14 bits are set to zero ...
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... IO0-19 110, 112, 113, 115-118, 121-123, 126-130, 133-137 DET0-1 81, 82 OER 74 OEREXT 76 OEI 78 OEIEXT 77 RND 75 6 HSP45116A I These inputs select the data to be output on RO0-19 and IO0-19. OUT OUT MUX MUX 1 0 RO16- Real CMAC Real CMAC 31-34 15- Real CMAC ...
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... Sine/Cosine Section (Sine/ Cosine Argument); the Time Accumulator supplies a pulse to mark the passage of a preprogrammed period of time. 7 HSP45116A The Phase Accumulator and Time Accumulator work on the same principle: a 32-bit word is added to the contents of a 32-bit accumulator register every clock cycle; when the sum ...
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... ACCUMULATOR ADDER CLK R.ENPHAC R.LOAD PACI TIME ACCUMULATOR REGISTER TIME 32 INCREMENT CLK > R.ENTIREG FIGURE 1. HSP45116A BLOCK DIAGRAM 16 ADDER SIN/COS ARGUMENT SINE/COSINE 16 GENERATOR CLK > 32 PHASE ACCUMULATOR PACO > PHASE ADDER ...
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... CLK < REG CLK > REG CLK 35 < REG CLK R.PEAK MUX FMT R.BINFMT R.SH(1:0) R.ENI OEI OEIEXT OER OEREXT OUTMUX(1:0) 4 RND RO(19-16) FIGURE 1. HSP45116A BLOCK DIAGRAM (Continued) 9 HSP45116A > 19 R.ENI R.SH(1:0) IMIN0-18 SHIFTER 16 CLK REG MUX R1.ACC CLK COMPLEX ACCUMULATOR REG MUX ...
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... Modulo π is used to calculate FFTs. This is explained in greater detail in the Applications Section. 10 HSP45116A The Phase Register adds an offset to the output of the Phase Accumulator. Since the Phase Register is only 16 bits added to the top 16 bits of the Phase Accumulator. ...
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... Multiplexer, the output of which is determined by the OUTMUX0- 1 lines (Table 4). BINFMT controls whether the output of the Multiplexer is presented in two’s complement or unsigned format; BINFMT = 0 inverts ROUT19 and IOUT19 for unsigned output, while BINFMT = 1 selects two’s complement. 11 HSP45116A OUT MUX The Complex Accumulator duplicates the accumulator in the CMAC ...
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... MSB ↑ Radix Point 12 HSP45116A SIN/COS INPUT ...
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... Rounding The operation of the HSP45116A is identical to the HSP45116 with the exception of a programmable rounding option added for the data outputs. The added functionality was achieved by using one of the HSP45116’s reserved Configuration Registers to specify rounding precision and replacing a V pin with a round enable (RND) input. When CC RND is “ ...
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... The resulting signal has components at twice the center frequency and at DC. Two HSP43220s, one each on the real and imaginary outputs of the HSP45116A, perform low pass filtering and decimation on the down converted data, resulting in a complex baseband signal. ...
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... CLK Low WR Low WR High Setup Time AD0- Hold Time AD0-1, CS from WR Setup Time C0- Hold Time C0-15 from WR 15 HSP45116A Thermal Information Thermal Resistance (Typical, Note 1) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG or ENTIREG is active always asynchronous when RND is active. AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. 16 HSP45116A ± = 5.0V 5 0°C to +70°C (Note 5) (Continued ...
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... Waveforms CLK MOD0-1 PACI CONTROL INPUTS RIN0-19 IIN0-19 ROUT0-19 IOUT0-19 DET0-1 PACO TICO CLK WR CS AD0-1 C0-15 17 HSP45116A MCH t MCS t t PCH PCS t t ECH ECS FIGURE 7. INPUT AND OUTPUT TIMING AWS t AWS t CWS FIGURE 8. CONTROL BUS TIMING ...
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... Waveforms (Continued) OER OEI OEREXT 1.5V OEIEXT t OE RO0-19 1.7V IO0-19 1.3V HIGH IMPEDANCE FIGURE 9. OUTPUT ENABLE, DISABLE TIMING 18 HSP45116A OUTMUX0-1 1. RO0-19 HIGH IO0-19 IMPEDANCE 2.0V 0. FIGURE 11. OUTPUT RISE AND FALL TIMES t MD FIGURE 10. MULTIPLEXER TIMING t RF FN4156.4 May 7, 2007 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 HSP45116A Q160.28x28 160 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYMBOL ...