hsp43891 Intersil Corporation, hsp43891 Datasheet
hsp43891
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hsp43891 Summary of contents
Page 1
... The output stage contains an additional 26-bit accumulator which can add the contents of any filter cell accumulator to the output stage accumulator shifted right by 8-bits. The HSP43891 has a maximum sample rate of 30MHz. The effective multiply-accumulate (mac) rate is 240MHz. The HSP43891 DF can be configured to process expanded coefficient and word sizes ...
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... V SUM13 SUM19 V SUM15 SUM12 SUM10 SUM8 SUM6 SUM20 SUM17 SUM16 HSP43891 SUM1 SUM3 SUM2 BOTTOM VIEW SUM0 PINS UP COUT2 CIN1 SS ALIGN DIENB DIN5 DIN4 PIN COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 DIN7 DIN6 DIN3 ...
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... SUM20 SUM19 SUM18 SUM17 SUM16 SUM15 SUM14 SUM13 SUM12 V SS SUM11 SUM10 SUM9 SUM8 SUM7 NC SUM6 3 HSP43891 100 LEAD MQFP TOP VIEW 100 ...
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... I DCM0-1 L1 HSP43891 NAME AND FUNCTION +5 power supply input. Power supply ground input. The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz. These nine inputs are the data sample input bus. Nine-bit data samples are synchronously loaded through these pins to the X register of each fi ...
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... COUT0-8 outputs of the right most cell to the COUT0-8 pins of the device. 5 HSP43891 NAME AND FUNCTION These 26 three-state outputs are used to output the results of the internal filter cell computations. Indi- vidual filter cell results or the result of the shift and add output stage can be output individual filter cell result output, the ADR0-2 signals select the fi ...
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... ERASE and RESET are latched and delayed one clock internally, clearing occurs on the second CLK following the onset of both ERASE and RESET low. 6 HSP43891 The second accumulator clearing mechanism clears a single accumulator in a selected cell. The cell select signal, CELLn, decoded from ADR0-2 and the ERASE signal enable clearing of the accumulator on the next CLK ...
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... LD CLR D1 REG D2 REG 1 MUX CLK D0-8 0 C0-8 X0-8 X CLR CLR 0-17 ACC.D0-25 CLR CELLn D Q CELLn LD CLK AOUT0-25 FIGURE 1. HSP43891 DF FILTER CELL LD CLR THREE-STATE BUFFERS ON CELL 7 ONLY D3 REG 1 MUX COUT0-8 CLK 0 COENB C MULTI- PLIER CORE P0-17 MREG0 CLK MREG1 SIGN EXTENSION ADDER ACC0-25 ACC CLK ...
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... SENBL Q D SENBH CLK FIGURE 2. HSP43891 DFP OUTPUT STAGE The 26 least significant bits (LSBs) from either a cell accumulator or the output buffer are output on the SUM0-25 bus. The output mux determines whether the cell accumulator selected by ADR0-2 or the output buffer is output to the bus. This mux is controlled by the SHADD input signal. Control is based on the state of the SHADD during two successive clocks ...
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... SAMPLE DATA 30MHz COUNTER CLOCK COEFF. RAM/ROM SYSTEM RESET ERASE FIGURE 3. HSP43891 30MHz, 8-TAP FIR FILTER APPLICATION SCHEMATIC 9 HSP43891 . . . HSP43891 . . . CELL 3 CELL ...
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... RESET SYSTEM RESET FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC 10 HSP43891 length and the internal pipeline delay of the DF. After the pipeline has filled, a new output sample is available every clock. The delay to last sample output from last sample input is Td. The output sums, Y timing diagram are derived from the sum-of-products equation ...
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... FIR, except the ERASE and SENBL/SENBH signals must be enabled independently for the two DFs in order to clear the correct accumulators and enable the SUM0-25 output signals at the proper times. TABLE HSP43891 , CELL 2 CELL 3 CELL ...
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... HSP43891 Decimation/Resampling The HSP43891 DF provides a mechanism for decimating by factors From the DF filter cell block diagram (Figure 1), note the three D registers and two multiplexers in the coefficient path through the cell. These allow the coefficients to be delayed clocks through the cell. The sequence table (Table 3) for a decimate-by-two fi ...
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... CIENB ADR0-2 DF0 SUM0-25 DF1 SUM0-25 SHADD DF0 SENBL/H DF1 SENBL/H DCM0-1 0 FIGURE 6. HSP43891 16-TAP 30MHz FILTER TIMING USING TWO CASCADED HSP43891s ...
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... TABLE 3. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER SEQUENCE; 30MHz IN, 15MHz OUT DATA SEQUENCE INPUT . . . X COEFFICIENT SEQUENCE INPUT . . . C CLK CELL 0 CELL 1 CELL ...
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... CIENB ADR0-2 DF0 SUM0-25 SHADD SENBL SENBH DCM0-1 1 FIGURE 7. HSP43891 16-TAP DECIMATE-BY-TWO FIR FILTER TIMING; 30MHz IN, 15MHz OUT ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 4. Output load per test load circuit and C 16 HSP43891 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . ...
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... Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. Test Load Circuit DUT † (NOTE) INCLUDES STRAY AND JIG CAPACITANCE NOTE: Switch S Open for I and I 1 CCSB CCOP 17 HSP43891 5V, 5 -20 (20MHz) TEST CONDITIONS MIN ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 18 HSP43891 CLK 3.0V INPUT† 2.0V 0.0V NOTE: Input includes:DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RE- SET, DCM0-1, ADR0-1, TCS, TCCI, SHADD ODS 1 ...