74lvq161 STMicroelectronics, 74lvq161 Datasheet

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74lvq161

Manufacturer Part Number
74lvq161
Description
Synchronous Presettable 4-bit Counter
Manufacturer
STMicroelectronics
Datasheet
DESCRIPTION
The
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
HIGH SPEED:
f
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
LOW NOISE:
V
75 TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
IMPROVED LATCH-UP IMMUNITY
MAX
CC
PLH
OH
OLP
CC
74LVQ161
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 180 MHz (TYP.) at V
= 0.3V (TYP.) at V
t
PHL
OL
= 12mA (MIN) at V
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
is
a
A
=25°C
CC
2
low
MOS technology. It is
= 3.3V
CC
CC
voltage
= 3.3 V
= 3.0 V
CMOS
Table 1: Order Codes
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (PE) and Count Enable Carry Input
(TE), determine the mode of operation as shown
in the Truth Table. A LOW signal on CLEAR
overrides counting and parallel loading and sets
all outputs on LOW state. A LOW signal on LOAD
overrides counting and allows information on
Parallel Data Qn inputs to be loaded into the
flip-flops on the next rising edge of CLOCK. With
LOAD and CLEAR, PE and TE permit counting
when both are high. Conversely, a LOW signal on
either PE and TE inhibits counting. All inputs and
outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
PACKAGE
TSSOP
SOP
SOP
74LVQ161
Rev. 2
74LVQ161MTR
74LVQ161TTR
TSSOP
T & R
1/14

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74lvq161 Summary of contents

Page 1

... Conversely, a LOW signal on either PE and TE inhibits counting. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LVQ161 SOP TSSOP PACKAGE T & R SOP 74LVQ161MTR TSSOP 74LVQ161TTR Rev. 2 1/14 ...

Page 2

... Figure 2: Input And Output Equivalent Circuit Table 3: Truth Table INPUTS CLEAR LOAD Don’t Care Logic level of data input; CARRY OUT Figure 3: Logic Diagram ...

Page 3

... Ground Current CC GND CC T Storage Temperature stg T Lead Temperature (10 sec) L Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied Parameter 74LVQ161 Value Unit - ...

Page 4

... Table 5: Recommended Operating Conditions Symbol V Supply Voltage (note Input Voltage I V Output Voltage O T Operating Temperature op Input Rise and Fall Time V dt/dv 1) Truth Table guaranteed: 1. from 0. Table 6: DC Specifications Symbol Parameter V High Level Input Volt. 3 Low Level Input Volt. ...

Page 5

... PLHn OSHL , Input 3ns Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min. 8.0 13.0 15.0 6.8 9.5 11.0 9.1 14.0 16.0 7.5 10.5 12.0 5.6 10.0 11.5 4.7 8.0 9.5 8.0 12.0 15.0 6.1 9.5 11.0 8.0 14.0 16.0 6.7 10.5 12.0 1.9 4.0 4.0 1.9 3.0 3.0 1.9 4.0 4.0 1.9 3.0 3.0 2.5 5.0 5.0 2.1 4.0 4.0 -1 -1.0 0.5 0.5 1.5 3.0 3.0 1.2 2.5 2.5 -0 -0.5 0.5 0.5 3.4 7.0 7.0 3.0 6.0 6 -0.6 0.5 0.5 150 80 60 180 100 80 0.5 1.0 1.0 0.5 1.0 1 PHLm PHLn 74LVQ161 Unit Max. 17.0 ns 12.5 18.5 ns 14.0 13.0 ns 10.5 17.0 ns 12.5 18 MHz 1.0 ns 1.0 5/14 ...

Page 6

... Table 9: Capacitive Characteristics Symbol Parameter C Input Capacitance IN C Power Dissipation PD Capacitance (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without PD load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I ...

Page 7

... Figure 7: Waveform - Propagation Delays Clear Mode (f=1MHz; 50% duty cycle) Figure 8: Waveform - Propagation Delays Preset Mode (f=1MHz; 50% duty cycle) 74LVQ161 7/14 ...

Page 8

... Figure 9: Waveform - Propagation Delays Countable Mode (f=1MHz; 50% duty cycle) Figure 10: Waveform - Propagation Delays Cascade Mode (f=1MHz; 50% duty cycle) 8/14 ...

Page 9

... 9 3.8 G 4 mm. TYP MAX. 1.75 0.25 0.004 1.64 0.46 0.013 0.25 0.007 0.5 45° (typ.) 10 0.385 6.2 0.228 1.27 8.89 4.0 0.149 5.3 0.181 1.27 0.019 0.62 8° (max.) 74LVQ161 inch MIN. TYP. 0.019 0.050 0.350 0016020D MAX. 0.068 0.010 0.063 0.018 0.010 0.393 0.244 0.157 0.208 0.050 0.024 9/14 ...

Page 10

... DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 4.9 E 6 0˚ PIN 1 IDENTIFICATION 1 10/14 TSSOP16 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 5 5.1 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.0079 0.193 0.197 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ ...

Page 11

... Tape & Reel SO-16 MECHANICAL DATA DIM. MIN 12 6.45 Bo 10.3 Ko 2.1 Po 3.9 P 7.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 6.65 0.254 10.5 0.406 2.3 0.082 4.1 0.153 8.1 0.311 74LVQ161 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.262 0.414 0.090 0.161 0.319 11/14 ...

Page 12

... Tape & Reel TSSOP16 MECHANICAL DATA DIM. MIN 12 6.7 Bo 5.3 Ko 1.6 Po 3.9 P 7.9 12/14 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 6.9 0.264 5.5 0.209 1.8 0.063 4.1 0.153 8.1 0.311 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.272 0.217 0.071 0.161 0.319 ...

Page 13

... Table 10: Revision History Date Revision 29-Jul-2004 2 Description of Changes Ordering Codes Revision - pag. 1. 74LVQ161 13/14 ...

Page 14

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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