74lv165apw NXP Semiconductors, 74lv165apw Datasheet - Page 2

• Manufacturer Part Number: 74lv165apw
• Description: 8-bit Parallel-in/serial-out Shift Register
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
DESCRIPTION
The 74LV165A is a high-performance, low-power,
low-voltage, Is-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 Jul 23
t
f
C
C
PHL
max
SYMBOL
Wide supply voltage range from 2.0 to 5.5 V
Complies with JEDEC standard:
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V)
JESD8-1A (4.5 to 5.5 V).
5.5 V tolerant inputs/outputs
CMOS LOW power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Asynchronous 8-bit parallel load
Synchronous serial input
Latch-up performance exceeds 250 mA
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
I
PD
8-bit parallel-in/serial-out shift register
P
f
f
C
V
N = total load switching outputs;
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per buffer
2
V
CE, CP to Q7, Q7
PL to Q7, Q7
D7 to Q7, Q7
CC
= 25 C.
f
o
2
) = sum of the outputs.
i
= GND to V
f
i
N + (C
PARAMETER
L
CC
.
V
CC
2
f
o
) where:
V
V
V
2
CC
CC
CC
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall times.
This device is fully specified for partial-power-down
applications using I
preventing the damaging current back flow through the
device when it is powered down.
The 74LV165A is an 8-bit parallel-load or serial-in shift
register with complementary serial outputs (Q7 and Q7)
available from the last stage. When the parallel-load input
(PL) is LOW, parallel data from the inputs D0 to D7 are
loaded into the register asynchronously. When input PL is
HIGH, data enters the register serially at the input DS and
shifts one place to the right (Q0 Q1 Q2, etc.) with each
positive-going clock transition. This feature allows
parallel-to-serial converter expansion by tying the output
Q7 to the input DS of the succeeding stage.
The clock input is a gate-OR structure which allows one
input to be used as an active LOW clock enable input (CE)
input. The pin assignment for the inputs CP and CE is
arbitrary and can be reversed for layout convenience. The
LOW-to-HIGH transition of the input CE should only take
place while CP HIGH for predictable operation.
D
= 3.3 V; C
= 3.3 V; C
= 3.3 V; notes 1 and 2
in W).
CONDITIONS
L
L
= 15 pF
= 15 pF
off
. The I
off
circuitry disables the output,
Product specification
7.5
8.0
8.5
115
3.0
24
TYPICAL
74LV165A
ns
ns
ns
MHz
pF
pF
UNIT