74lvxz161284 Fairchild Semiconductor, 74lvxz161284 Datasheet
74lvxz161284
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74lvxz161284 Summary of contents
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... Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 74LVXZ161284MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [RAIL] 74LVXZ161284MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] © 2002 Fairchild Semiconductor Corporation Features ...
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Logic Symbol Connection Diagram www.fairchildsemi.com Pin Descriptions Pin Names Description HD High Drive Enable Input (Active HIGH) DIR Direction Control Input A –A Inputs or Outputs –B Inputs or Outputs –A Inputs 9 13 ...
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Logic Diagrams FIGURE 1. Input Detection Circuit Timing Input Detection Circuit 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings Supply Voltage CC—Cable V Must Be ≥ V CC—Cable CC Input Voltage (V )—(Note –A , PLH , DIR, HD − 0. – ...
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DC Electrical Characteristics Symbol Parameter V Maximum LOW A , HLH OL n Level Output Voltage PLH PLH R Maximum Output ...
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AC Electrical Characteristics Symbol Parameter Min t A – –B 2.0 PHL – –B 2.0 PLH – –A 2.0 PHL 1 8 ...
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AC Loading and Waveforms Pulse Generator for all pulses: Rate ≤ 1.0 MHz; Z FIGURE 2. Port and Propagation Delay Waveforms FIGURE 3. Port and Output Waveforms FIGURE ...
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AC Loading and Waveforms FIGURE 5. Port and Slew Test Load and Waveforms FIGURE 6. Port and Slew Test Load and Waveforms www.fairchildsemi.com (Continued) 8 ...
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AC Loading and Waveforms t = Output Rise Time, Open Drain Output Fall Time, Open Drain f FIGURE 7. Ports and Rise and Fall Test Load and Waveforms for Open Drain ...
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AC Loading and Waveforms FIGURE 9. t PZH FIGURE 10. t www.fairchildsemi.com (Continued) and t Test Load and Waveforms, DIR to A PZL and t Test Load and Waveforms PHZ PLZ DIR to B – –A 1 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 11 www.fairchildsemi.com ...