74lvx174 STMicroelectronics, 74lvx174 Datasheet

no-image

74lvx174

Manufacturer Part Number
74lvx174
Description
Low Voltage Cmos Hex D-type Flip-flop With Clear With 5v Tolerant Inputs
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74lvx174M
Manufacturer:
ST
0
Part Number:
74lvx174MTC
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
74lvx174MTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
Part Number:
74lvx174MX
Manufacturer:
TI
Quantity:
1 000
Part Number:
74lvx174TTR
Manufacturer:
ST
0
LOW VOLTAGE CMOS HEX D-TYPE FLIP-FLOP WITH CLEAR
DESCRIPTION
The 74LVX174 is a low voltage CMOS HEX
D-TYPE
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
HIGH SPEED:
f
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL:
V
LOW POWER DISSIPATION:
I
LOW NOISE:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
MAX
CC
PLH
OH
IL
OLP
CC
=0.8V, V
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 3.6V (1.2V Data Retention)
= 180MHz (TYP.) at V
= 0.3V (TYP.) at V
t
PHL
FLIP
OL
= 4mA (MIN)
IH
=2V at V
FLOP
CC
A
WITH
=25°C
CC
=3V
CC
= 3.3V
= 3.3V
CLEAR
2
MOS
NON
WITH 5V TOLERANT INPUTS
Table 1: Order Codes
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
74LVX174
Rev. 3
74LVX174MTR
74LVX174TTR
TSSOP
T & R
1/12

Related parts for 74lvx174

74lvx174 Summary of contents

Page 1

... Data Retention) CC PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C technology ideal for low power, battery operated and low noise 3 ...

Page 2

... Figure 2: Input Equivalent Circuit Table 3: Truth Table INPUTS CLEAR Don’t Care Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/12 Table 2: Pin Description PIN N° 10, 12 11, 13 CLOCK ...

Page 3

... Value -55 to 125 0 to 100 Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min. 1.5 1.5 2.0 2.0 2.4 2.4 0.5 0.5 0.8 0.8 0.8 0.8 2.0 1.9 1.9 3.0 2.9 2.9 2.48 2.4 0.0 0.1 0.1 0.0 0.1 0.1 0.36 0.44 0 74LVX174 Unit °C °C Unit °C ns/V Unit Max. V 0.5 0.8 V 0.8 V 0.1 0 3/12 ...

Page 4

... Table 7: Dynamic Switching Characteristics Symbol Parameter V Dynamic Low Voltage OLP Quiet Output (note OLV V Dynamic High Voltage IHD Input (note Dynamic Low Voltage ILD Input (note Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. ...

Page 5

... T OUT Figure 5: Waveform - Propagation Delays (f=1MHz; 50% duty cycle) Test Condition (V) Min. 3 10MHz 3.3 IN Value = 25°C -40 to 85°C -55 to 125°C A Typ. Max. Min. Max. Min CC(opr 74LVX174 Unit Max (per circuit 5/12 ...

Page 6

... Figure 6: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Recovery Time, Minimum Pulse Width (f=1MHz; 50% duty cycle) 6/12 ...

Page 7

... 9 3.8 G 4 mm. TYP MAX. 1.75 0.25 0.004 1.64 0.46 0.013 0.25 0.007 0.5 45° (typ.) 10 0.385 6.2 0.228 1.27 8.89 4.0 0.149 5.3 0.181 1.27 0.019 0.62 8° (max.) 74LVX174 inch MIN. TYP. 0.019 0.050 0.350 0016020D MAX. 0.068 0.010 0.063 0.018 0.010 0.393 0.244 0.157 0.208 0.050 0.024 7/12 ...

Page 8

... DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 4.9 E 6 0˚ PIN 1 IDENTIFICATION 1 8/12 TSSOP16 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 1 1.05 0.30 0.20 5 5.1 6.4 6.6 4.4 4.48 0.65 BSC 8˚ 0.60 0. inch MIN. TYP. 0.002 0.004 0.031 0.039 0.007 0.004 0.0079 0.193 0.197 0.244 0.252 0.169 0.173 0.0256 BSC 0˚ ...

Page 9

... Tape & Reel SO-16 MECHANICAL DATA DIM. MIN 12 6.45 Bo 10.3 Ko 2.1 Po 3.9 P 7.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 6.65 0.254 10.5 0.406 2.3 0.082 4.1 0.153 8.1 0.311 74LVX174 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.262 0.414 0.090 0.161 0.319 9/12 ...

Page 10

... Tape & Reel TSSOP16 MECHANICAL DATA DIM. MIN 12 6.7 Bo 5.3 Ko 1.6 Po 3.9 P 7.9 10/12 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 6.9 0.264 5.5 0.209 1.8 0.063 4.1 0.153 8.1 0.311 inch MIN. TYP. MAX. 12.992 0.519 0.882 0.272 0.217 0.071 0.161 0.319 ...

Page 11

... Table 10: Revision History Date Revision 27-Aug-2004 3 Description of Changes Ordering Codes Revision - pag. 1. 74LVX174 11/12 ...

Page 12

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

Related keywords