74lvx132mx-nl Fairchild Semiconductor, 74lvx132mx-nl Datasheet

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74lvx132mx-nl

Manufacturer Part Number
74lvx132mx-nl
Description
74lvx132 Low Voltage Quad 2-input Nand Schmitt Trigger
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
74LVX132M
74LVX132SJ
74LVX132MTC
74LVX132MTCX_NL
(Note 1)
74LVX132
Low Voltage Quad 2-Input NAND Schmitt Trigger
General Description
The LVX132 contains four 2-input NAND Schmitt Trigger
Gates. The pin configuration and function are the same as
the LVX00 but the inputs have hysteresis between the pos-
itive-going and negative-going input thresholds, which are
capable of transforming slowly changing input signals into
sharply defined, jitter-free output signals, thus providing
greater noise margins than conventional gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Diagram
Pin Descriptions
Order Number
Package
Number
MTC14
MTC14
M14A
M14D
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names
A
DS012159
n
Y
, B
n
n
Features
Connection Diagram
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Descriptions
Package Description
Outputs
Inputs
October 1996
Revised February 2005
www.fairchildsemi.com

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74lvx132mx-nl Summary of contents

Page 1

... Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Diagram Pin Descriptions © 2005 Fairchild Semiconductor Corporation Features Input voltage level translation from Ideal for low power/low noise 3.3V applications ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. Input Voltage ( Output Diode Current ( 0. 0.5V ...

Page 3

AC Electrical Characteristics V CC Symbol Parameter (V) t Propagation 2.7 PLH t Delay Time PHL r 3.3 0.3 t Output to Output 2.7 OSLH t Skew (Note 5) 3.3 OSHL Note 5: Parameter guaranteed by design OSLH ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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