74lvcz161284a STMicroelectronics, 74lvcz161284a Datasheet

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74lvcz161284a

Manufacturer Part Number
74lvcz161284a
Description
Low Voltage High Speed Ieee 1284 Transceiver With Error-free Power-up
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The 74LVCZ161284A contains eight high speed
non inverting bidirectional buffers and eleven
control/status non-inverting buffers with open
drain outputs fabricated in silicon gate C
technology. It’s intended to provide a standard
signaling method for a bi-direction parallel
peripheral in an Extended Capabilities Port Mode
(ECP). The HD (Active HIGH) input pin enables
the Cable port to switch from Open Drain to a high
drive totem pole output, capable of sourcing 14mA
on all thirteen buffer and 84mA on PERI LOGIC
OUTPUT buffer. The DIR input determines the
direction of data flow on the bidirectional buffers.
DIR (Active HIGH) enables data flow from A port
to B port. DIR (Active LOW) enables data flow
from B port to A port. The Y output (Y9-Y13) stay
in the high state after power-on until an associated
input A9-A13) goes high. When an associated
input goes high, all Y outputs are active, and non
July 2005
HIGH SPEED: t
LOW POWER DISSIPATION:
I
TTL COMPATIBLE INPUTS
V
OPERATING VOLTAGE RANGE:
V
A PORT HAVE STANDARD 4mA TOTEM
POLE OUTPUT
B PORT HIGH DRIVE SOURCE/SINK
CAPABILITY OF 14mA
AUTO POWER-UP FEATURE TO PREVENT
PRINTER ERRORS
SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR
BIDIRECTIONAL PARALLEL
COMMUNICATIONS BETWEEN PERSONAL
COMPUTER ANT PRINTING PERIPHERALS
TRANSLATION CAPABILITY ALLOW
OUTPUTS ON CABLE SIDE TO INTERFACE
WITH 5V SIGNAL
PULL-UP RESISTOR INTEGRATED ON ALL
OPEN-DRAIN OUTPUT ELIMINATE THE
NEED FOR DISCRETE RESISTOR
REPLACE THE FUNCTION OF TWO
74LVC1284 DEVICES
CC
IH
CC
=20µA (MAX) at V
=2V (MIN) V
(OPR) = 3.0V to 3.6V
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
PD
IL
=0.8(MAX)
= 9ns (MAX.) at V
CC
=3.6V T
A
=85°C
CC
= 3V
2
MOS
WITH ERROR-FREE POWER-UP
ORDER CODES
PIN CONNECTION
PACKAGE
TSSOP
74LVCZ161284A
TUBE
TSSOP
74LVCZ161284ATTR
T & R
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74lvcz161284a Summary of contents

Page 1

... NEED FOR DISCRETE RESISTOR REPLACE THE FUNCTION OF TWO I 74LVC1284 DEVICES DESCRIPTION The 74LVCZ161284A contains eight high speed non inverting bidirectional buffers and eleven control/status non-inverting buffers with open drain outputs fabricated in silicon gate C technology. It’s intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP) ...

Page 2

... Y outputs. This special feature prevents printer system errors deasserting the BUSY signal in the cable at LOGIC DIAGRAM NOTE A: The PMOS transistors prevent backdriving current from the signal pins to V PMOS transistor is turned off when the associated driver is in the low state. ...

Page 3

... HD L B1-B8 Data to A1-A8 A9-A13 Data to Y9-Y13 C14-C17 Data to A14-A17 H L A1-A8 Data to B1-B8 A9-A13 Data to Y9-Y13 C14-C17 Data to A14-A17 H 74LVCZ161284A NAME AND FUNCTION OUTPUT Y9-Y13 and PLO Open Drain Y9-Y13 and PLO Totem Pole B1-B8 Y9-Y13 and PLO Open Drain B1-B8 Y9-Y13 and PLO Totem Pole ...

Page 4

... ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage CC Cable Supply Voltage (must be ≥ CCcable V DC Input Voltage A1-A13 Input Voltage B1-B8, C14-C17 Input Voltage B1-B8, C14-C17, HL IBp V DC Output Voltage A1-A8, A14-A17 Output Voltage B1-B8, Y9-Y13 Output Voltage B1-B8, Y9-Y13, PL ...

Page 5

... IN 3.6 5.5 3.0 3.0 3.0 3.0 3.0 3.0 3.0 4.5 3.15 3.15 3.0 3.0 3.0 3.0 3.0 3.0 3.0 4.5 3.0 3.0 3.0 4.5 3.6 3.6 V 3.6 3.6 3.6 5.0 3.6 5.0 V 3.6 5.0 V 3.6 3.6 3.6 5.0 V 3.6 3 5.0 , DIR, HD 3.3 5.0 IN 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 74LVCZ161284A Value - °C Min. Max. 2 2.3 2.6 0.8 0.8 1.6 I =-50µA 2 =-4mA 2 =-14mA 2 =-14mA 2. =-500µA 3 =50µA 0 =4mA 0 =14mA 0 =14mA 0. =84mA 0. =84mA 0. =GND (Pull-up res) -3.5 I ± ...

Page 6

... AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Propagation A1-A8 to B1-B8, PLH Delay Time A9-A13 to Y9-Y13 t PHL B1-B8 to A1-A8, C14-C17 to A14-A17 Enable Delay DIR to A PZH Time Bn, Y9-Y13 PZL t Disable Delay DIR to A PLZ Time t DIR to A PHZ HD to Bn, Y9-Y13 t t Rise and Fall Time ...

Page 7

... R1 = 500Ω or equivalent pulse generator (typically 50Ω) T OUT WAVEFORM 1: ERROR-FREE CIRCUIT TIMING CHART (f=1MHz; 50% duty cycle) TEST to PLH) (see waveform PLH B1-B8, Y9-Y13, PLH HLH) (see waveform 3) IN 74LVCZ161284A Open CC CC Open GND GND GND GND Open ...

Page 8

... WAVEFORM 2: PROPAGATION DELAY INPUT An TO OUTPUT (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY INPUT Bn TO OUTPUT (f=1MHz; 50% duty cycle 50 74LVCZ161284A 8/12 ...

Page 9

... WAVEFORM 4: DATA TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) WAVEFORM 5: DIR TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74LVCZ161284A 9/12 ...

Page 10

... DIM. MIN 0. 0.17 c 0. 0° PIN 1 IDENTIFICATION 1 10/12 TSSOP48 MECHANICAL DATA mm. TYP MAX. 1.2 0.15 0.9 0.27 0.20 12.6 8.1 BSC 6.2 0.5 BSC 8° 0. inch MIN. TYP. 0.002 0.035 0.0067 0.0035 0.0079 0.488 0.318 BSC 0.236 0.0197 BSC 0° 0.018 7065588D MAX ...

Page 11

... Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 13.3 0.516 1.7 0.059 4.1 0.153 12.1 0.468 74LVCZ161284A inch TYP. MAX. 12.992 0.519 1.197 0.350 0.524 0.067 0.161 0.476 11/12 ...

Page 12

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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