74lvc543a NXP Semiconductors, 74lvc543a Datasheet - Page 2

• Manufacturer Part Number: 74lvc543a
• Description: Octal D-type Registered Transceiver 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2004 Apr 07
t
C
C
C
PHL
SYMBOL
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B/JESD36
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
3-state non-inverting outputs for bus oriented
applications
High-impedance when V
ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 C to +85 C and 40 C to +125 C.
I
I/O
PD
Octal D-type registered transceiver; 3-state
P
f
f
C
V
N = total load switching outputs;
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay An to Bn; Bn to An
input capacitance
input/output capacitance
power dissipation capacitance per latch
2
V
CC
= 25 C; t
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
CC
r
= t
PARAMETER
= 0 V
f
2.5 ns.
L
CC
.
V
CC
2
f
o
) where:
2
C
V
CC
L
DESCRIPTION
The 74LVC543A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
The 74LVC543A is an octal registered transceiver
containing two sets of D-type latches for temporary
storage of the data flow in either direction. Separate latch
enable inputs (pins LE
inputs (pins OE
register to permit independent control of inputting and
outputting in either direction of the data flow.
The 74LVC543A contains eight D-type latches, with
separate inputs and controls for each set. For data flow
from pins A to B, for example, the A to B enable input
(pin E
A0 to A7 or take data from pins B0 to B7, as indicated in
the “Function table”. With pin E
the A to B latch enable input (pin LE
latches transparent; a subsequent LOW-to-HIGH
transition on pin LE
where it is stored and the B outputs no longer change with
the A inputs. With pins E
3-state B output buffers are active and display the data
present at the outputs of the A latches.
outputs enabled
outputs disabled
= 50 pF; V
D
= 3.3 V; notes 1 and 2
in W).
AB
CONDITIONS
) must be LOW in order to enter data from pins
CC
= 3.3 V
AB
and OE
AB
puts the A data into the latches
AB
AB
and LE
BA
and OE
) are provided for each
AB
3.0
4.0
5.0
15.0
3.0
BA
TYPICAL
LOW, a LOW signal on
Product specification
) and output enable
AB
AB
74LVC543A
both LOW, the
) makes the A to B
ns
pF
pF
pF
pF
UNIT