74lvch32373a NXP Semiconductors, 74lvch32373a Datasheet - Page 2

• Manufacturer Part Number: 74lvch32373a
• Description: 32-bit Transparent D-type Latch With 5 V Tolerant Inputs/outputs; 3-state
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FEATURES
DESCRIPTION
The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device superior to most
advanced CMOS compatible TTL families.
The inputs can be driven from either 3.3 V or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed
3.3 V and 5 V environment.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2004 May 19
t
t
t
C
C
PHL
PZH
PHZ
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-trough standard pin-out architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
All data inputs have bushold
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM EIA/JESD22-A114-B exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 C to +85 C
Packaged in plastic fine-pitch ball grid array package.
I
PD
32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state
SYMBOL
P
f
f
i
o
/t
/t
/t
D
PD
= input frequency in MHz;
PLH
PZL
PLZ
= output frequency in MHz;
= C
is used to determine the dynamic power dissipation (P
PD
amb
V
CC
= 25 C; t
propagation delay nDn to nQn
propagation delay nLE to nQn
3-state output enable time nOE to nQn
3-state output disable time nOE to nQn
input capacitance
power dissipation per latch
2
f
i
N + (C
r
= t
f
PARAMETER
2.5 ns
L
V
CC
2
f
o
) where:
2
The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One latch enable
input (nLE) and one output enable input (nOE) are
provided for each octal. Inputs can be driven from either
3.3 V or 5 V devices.
The 74LVCH32373A consists of 4 sections of eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nDn inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.
When input nLE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.
The 74LVCH32373A bushold data input circuits eliminate
the need for external pull-up resistors to hold unused
inputs.
C
C
C
C
V
D
CC
L
L
L
L
outputs enabled
outputs disabled
in W).
= 50 pF; V
= 50 pF; V
= 50 pF; V
= 50 pF; V
= 3.3 V; notes 1 and 2
CONDITIONS
CC
CC
CC
CC
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
74LVCH32373A
3.0
3.4
3.5
3.9
5.0
15
11
TYPICAL
Product specification
ns
ns
ns
ns
pF
pF
pF
UNIT