74lvc2g125dc NXP Semiconductors, 74lvc2g125dc Datasheet
74lvc2g125dc
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74lvc2g125dc Summary of contents
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Dual bus buffer/line driver; 3-state Rev. 08 — 7 September 2007 1. General description The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level ...
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... Temperature range Name 74LVC2G125DP +125 C 74LVC2G125DC +125 C 74LVC2G125GT +125 C 74LVC2G125GM +125 C 4. Marking Table 2: Marking codes Type number 74LVC2G125DP 74LVC2G125DC 74LVC2G125GT 74LVC2G125GM 5. Functional diagram 74LVC2G125 1A 1OE 2A 2OE Fig 1. Logic symbol 74LVC2G125_8 Product data sheet Description TSSOP8 plastic thin shrink small outline package; 8 leads; ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration TSSOP8 and VSSOP8 74LVC2G125 1OE GND 4 Transparent top view Fig 4. Pin configuration XSON8 6.2 Pin description Table 3: Pin description Symbol Pin TSSOP8; VSSOP8 XSON8 1OE GND ...
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... NXP Semiconductors 7. Functional description [1] Table 4: Function table Control nOE HIGH voltage level LOW voltage level don’t care high-impedance OFF-state 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0 V). ...
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... NXP Semiconductors 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter [ +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current ...
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... NXP Semiconductors Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current I I OFF-state output current ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see enable time nOE to nY; see disable time nOE to nY; see dis ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in Logic levels: V and V are typical output voltage levels that occur with the output load Fig 6. Propagation delay input (nA) to output (nY) nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in ...
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... NXP Semiconductors Test data is given in Table 10. Definitions for test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test voltage for switching times. EXT Fig 8. Load circuitry for switching times ...
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... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC SOT902 Fig 12 ...
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... Revision history Document ID Release date 74LVC2G125_8 20070907 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • In current. 74LVC2G125_7 20060523 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 14 Abbreviations ...