clc031 National Semiconductor Corporation, clc031 Datasheet
clc031
Available stocks
Related parts for clc031
clc031 Summary of contents
Page 1
... The unique multi-functional I/O port of the CLC031 provides external access to functions and data stored in the configu- ration and control registers. This feature allows the designer greater flexibility in tailoring the CLC031 to the desired ap- plication. The CLC031 is auto-configured to a default oper- ating condition at power-on or after a reset command. Sepa- ...
Page 2
Typical Application www.national.com 2 20020101 ...
Page 3
Block Diagram 3 20020102 www.national.com ...
Page 4
... Connection Diagram www.national.com 64-Pin TQFP Order Number CLC031VEC See NS Package Number VEC-64A 4 20020103 ...
Page 5
Absolute Maximum Ratings It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace speci- fied devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. CMOS I/O ...
Page 6
Required Input Conditions Symbol Parameter Ancilliary / Control Data f ACLK Clock Frequency Ancilliary / Control Clock DC ACLK Duty Cycle Ancilliary / Control Clock and Data Rise Time, Fall r f Time Setup Time ...
Page 7
AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Serial Video Data Inputs BR Serial Input Data Rate SDI Rise Time, Fall Time r f Parallel Video Data Outputs ...
Page 8
... Note 9: Required Input Conditions are the electrical signal conditions or component values which shall be supplied by the circuit in which this device is used in order for it to produce the specified DC and AC electrical output characteristics. Note 10: Functional and certain other parametric tests utilize a CLC030 as the input source to the SDI inputs of the CLC031. The CLC030 is DC coupled to the inputs of the CLC031. Typical V ...
Page 9
Test Circuit 9 20020107 www.national.com ...
Page 10
... Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps. Corresponding parallel output data rates are 27.0 MHz, 36.0 MHz, 54.0 MHz, 74.176MHz and 74.25 MHz. The CLC031 accepts ECL or LVDS serial data input signals. Outputs signals are compatible with LVCMOS logic devices. Note: In the following explanations, these logical equiva- ≡ ...
Page 11
... The CLC031 may be configured to operate in a single video format by loading the appropriate FORMAT SET[4:0] control data into the FORMAT 0 control register. Also, the CLC031 ...
Page 12
... AD[9:8] must be driven as 00b. The complete address word will be 0XXh, where 0 is AD[9:8] and XX are AD[7:0]. The address is captured on the rising edge of A control data is being read from the port, the CLC031 will output AD[9:8] as 10b (2XXh, where XX are output data AD[7:0]) and may be ignored by the monitoring system. Data ...
Page 13
... Ancilliary Data Flag, a 3-word Data ID and Data Count, 255 8- or 10-bit User Data Words and a Checksum. The design of the CLC031 Ancilliary Data FIFO also allows storage shorter length messages with total length not exceeding 259 words including all ID information. Ancil- liary Data is copied from the data stream into the Ancilliary Data FIFO ...
Page 14
... Toggle A 5. Present 310h to AD[9:0] as the register data. 6. Toggle A EDH/CRC SYSTEM The CLC031 has EDH and CRC character generation and checking circuitry. The EDH system functions as described in SMPTE Recommended Practice RP-165. The CRC sys- tem functions as specified in SMPTE 292M. The EDH/CRC ...
Page 15
... Refer to Figure 6 for a typical load circuit and connection information. The CLC031 indicates that the PLL is locked to the incoming data rate and that the CDR has acquired a phase of the serial data by setting the Lock Detect bit in the Video Info 0 control register ...
Page 16
... If no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals after TPG Enable is set. If errors have been detected in the internal circuitry of the CLC031, Pass/Fail will remain reset to a logic-0. TPG or BIST operation is stopped by resetting the TPG Enable bit. Parallel output data is present at the DV[19:0] outputs during TPG or BIST operation ...
Page 17
Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary Register Function Bits EDH and CRC Operations CRC Error (SD/HD) 1 CRC Error Luma 1 CRC Error Chroma 1 CRC Replace 1 Full-Field Flags 5 Active Picture Flags 5 ...
Page 18
Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary (Continued) Register Function Bits Sync Detect Enable 1 De-Dither Enable 1 Vert. De-Dither Enable 1 Lock Detect 1 Unscrambled 1 Video Data Out TPG and BIST Operations Test Pattern ...
Page 19
Device Operation (Continued) TABLE 2. Control Register Bit Assignments (Continued) Bit 7 Bit 6 ANC FIFO SHORT MSG ANC PARITY 90% FULL DETECT FORMAT 0 (register address 0Bh) FRAMING SD ONLY HD ONLY MODE FORMAT 1 (register address 0Ch) F ...
Page 20
... CHROMA bits. The CRC REPLACE bit, when set, causes the CRCs in the Address incoming data to be replaced with CRCs calculated by the Hexadecimal CLC031. The bit is normally reset (OFF). 01 EDH 2 (register 03h) 02 The EDH Ancilliary Data flags ANC UES, ANC IDA, ANC ...
Page 21
... CLK FIFO is in use. Otherwise, message tracking and related functions will not operate correctly. The CLC031 can keep track ANC data packets in the ANC FIFO. Incoming packet length versus available space in the FIFO is also tracked. The MSG TRACK bit in the control registers, when set, enables tracking of packets in the FIFO ...
Page 22
... SMPTE 274 10100 HDTV, 74.25 SMPTE 296 (1, 2) The HD Only bit when set to a logic-1 locks the CLC031 into the high definition data range and frequency. In systems designed to handle only high definition signals, enabling HD Only reduces the time required for the CLC031 to establish frequency lock and determine the HD format being pro- cessed ...
Page 23
Device Operation (Continued) > Test Pattern Select Word Bits Video Raster Standard 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black PLL Path. EQ Path. Colour Bars 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 274M) ...
Page 24
... D-to-A converters and picture monitors. The CLC031 incorporates circuitry that implements a method for handling data that has been subjected to LSB dithering. Data from the de-scrambler is routed for de- dithering ...
Page 25
... The CLKEN bit when reset to a logic-0 enables the oscillator signal to be used by the CLC031 as a reference. The default state of this bit at power-on is enabled. In general, this function and bit should not be disabled. The INT_OSC EN bit enables the internal crystal oscillator amplifier ...
Page 26
Device Operation (Continued) TABLE 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping Register Bit [5] reserved 0 FF Flag Error 0 AP Flag Error 0 ANC Flag Error 0 CRC Error (SD/HD) 0 ANC FIFO 90% ...
Page 27
Pin Descriptions Pin Name 1 AD9 2 AD8 3 AD7 4 AD6 5 AD5 6 V SSD 7 AD4 8 AD3 9 AD2 10 AD1 11 AD0 12 V DDD 13 A CLK 14 IO7 15 IO6 16 IO5 17 ...
Page 28
... In especially noisy power supply environments, such as is often the case when using switching power supplies, sepa- rate filtering may be used at the CLC031’s PLL and serial input power pins. The CLC031 was designed for this situa- tion. The I/O, digital section, PLL and serial input power supply feeds are independent (see pinout description table and pinout drawing for details) ...
Page 29
... CRC processing are disabled and ANC data extraction will not function. Output video chroma and luma data will be word-aligned. Post-processing of the par- allel data output from the CLC031 will be needed to imple- ment CRC checking or line number tracking. USING EXTERNAL VCXO FOR VCLK ...
Page 30
... AND gate output connected to the OE pin of the NC7SZ125. This circuit uses the 27.00MHz VCXO as default and en- ables the 74.25MHz VCXO when a valid high-definition sig- nal is present. The outputs from the buffers are daisy- chained together and sent to the CLC031’ other devices, such as the CLC030 serializer. 30 20020114 ...
Page 31
... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) 64-Pin TQPF Order Number CLC031VEC NS Package Number VEC-64A 2. A critical component is any component of a life ...