MC14027BDG ON Semiconductor, MC14027BDG Datasheet - Page 6

• Manufacturer Part Number: MC14027BDG
• Description: IC FLIP-FLOP J-K DUAL 16-SOIC
• Manufacturer: ON Semiconductor
• Series: 4000Br
• Type: JK Typer

Specifications of MC14027BDG

• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 13MHz
• Delay Time - Propagation: 50ns
• Trigger Type: Positive Edge
• Voltage - Supply: 3 V ~ 18 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Package: 16SOIC
• Logic Function: JK-Type
• Logic Family: 4000
• Number Of Element Outputs: 1
• Number Of Elements Per Chip: 2
• Input Signal Type: Single-Ended
• Output Signal Type: Differential
• Set/reset: Set/Reset
• Typical Operating Supply Voltage: 3.3|5|9|12|15 V
• Technology: CMOS
• Number Of Bits: 2
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Invert/Non-Invert
• Operating Supply Voltage (typ): 3.3/5/9/12/15V
• Package Type: SOIC
• Propagation Delay Time: 450ns
• Low Level Output Current: 4.2mA
• High Level Output Current: -4.2mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 18V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Compliant
• Other names: MC14027BDGOS

20 ns
C
K
J
Q
Inputs R and S low.
For the measurement of t
the Inputs J and K are kept high.
Figure 1. Dynamic Signal Waveforms
t
WH
t
t
PLH
TLH
S
K
R
J
10%
50%
(J, K, Clock, and Output)
90%
t
su
C
20 ns
50%
10%
90%
f
1
cl
20 ns
20 ns
WH
10%
50%
90%
, I/f
10%
90%
C
cl
t
su
t
WL
, and P
50%
t
PHL
t
t
THL
h
20 ns
D
20 ns
C
C
C
V
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
OH
OL
(1/2 of Device Shown)
http://onsemi.com
LOGIC DIAGRAM
MC14027B
6
C
C
SET OR
RESET
CLOCK
Q or Q
C
C
20 ns
Figure 2. Dynamic Signal Waveforms
90%
t
w
t
t
PLH
PHL
(Set, Reset, Clock, and Output)
50%
20 ns
50%
90%
10%
20 ns
C
C
50%
t
t
w
rem
Q
10%
Q
20 ns
V
V
V
V
V
V
DD
SS
DD
SS
OH
OL