hd74ls192 Renesas Electronics Corporation., hd74ls192 Datasheet

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hd74ls192

Manufacturer Part Number
hd74ls192
Description
Synchronous Up / Down Decade Counter Dual Clock Lines
Manufacturer
Renesas Electronics Corporation.
Datasheet

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hd74ls192P
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HD74LS192
Synchronous Up / Down Decade Counter (dual clock lines)
Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change
coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output
counting spikes which are normally associated with asynchronous (ripple clock) counters. The outputs of the four
master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of
counting is determined by which count input is pulsed while the other count input is high. This counter is fully
programmable; that is, each output may be preset to either level by desired data at the data inputs while the load inputs
is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input
has been provided which forces all outputs to the low level when a high level is applied. The clear function is
independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements.
This reduces the number of clock drivers, etc., required for long words. This counter was designed to be cascaded
without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-and down-
counting functions.
The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly,
the carry output produces a pulse equal in width to the count up input when an overflow condition exists.
The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs
respectively of .the succeeding counter.
Features
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 10
Part Name
HD74LS192P
HD74LS192FPEL
Ordering Information
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
P
FP
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
REJ03D0454–0200
Feb.18.2005
Rev.2.00

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hd74ls192 Summary of contents

Page 1

... The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of .the succeeding counter. Features Ordering Information Part Name Package Type HD74LS192P DILP-16 pin HD74LS192FPEL SOP-16 pin (JEITA) Note: Please consult the sales office for the above package availability. Rev.2.00, Feb.18.2005, page Package Code Package (Previous Code) Abbreviation ...

Page 2

... HD74LS192 Pin Arrangement Data B Input Outputs Count Down Inputs Count Up Outputs GND Rev.2.00, Feb.18.2005, page Clear Count 4 Borrow Down Count 5 Carry Load (Top view ...

Page 3

... HD74LS192 Block Diagram Data Input A Down Count Up Count Data Input B Data Input C Data Input D Clear Load Absolute Maximum Ratings Item Supply voltage Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.2.00, Feb.18.2005, page ...

Page 4

... HD74LS192 Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Pulse width Setup time (Clear) Setup time Hold time Electrical Characteristics Item Symbol V IH Input voltage Output voltage Input current Short-circuit output ...

Page 5

... HD74LS192 Count Sequence Clear Load A B Data Inputs C D Count Up Count Down Carry Borrow Sequence 0 Illustrated Clear Preset Rev.2.00, Feb.18.2005, page Count Count Down ...

Page 6

... HD74LS192 Testing Method Test Circuit 4.5V Input P. 50Ω out Notes includes probe and jig capacitance All diodes are 1S2074(H). Testing Table Item From input to output max Up Count t Down Count PLH t Load Q PHL Clear Q Note: *. For initialized Item From input to output ...

Page 7

... HD74LS192 Waveforms (Count Up) max PLH PHL t TLH 90% Count 1.3V 1.3V Up 10% t PLH (Measure Outputs (Measure before 1 clock Carry Notes: 1. Input pulse TLH Duty cycle = 50% 2. for max TLH THL reference bit time when all outputs are low. ...

Page 8

... HD74LS192 Waveforms (Count Down) max PLH PHL t TLH Count 90% 90% Down 10% 10 Outputs Borrow Notes: 1. for max TLH THL reference bit time when all outputs are high. n Rev.2.00, Feb.18.2005, page THL ...

Page 9

... HD74LS192 Waveforms (Load, Clear Q) PLH PHL t TLH Clear 10% Data Inputs ( Load Q Note: Input pulse ns, t TLH Rev.2.00, Feb.18.2005, page THL 90% 90% 1.3V 1.3V 10% t TLH t w (CLR) 20ns 90% 1.3V 10 THL 90% 1.3V 1.3V 10 PHL PLH 1.3V 1. THL ...

Page 10

... HD74LS192 Package Dimensions JEITA Package Code RENESAS Code P-DIP16-6.3x19.2-2.54 PRDP0016AE 0. JEITA Package Code RENESAS Code P-SOP16-5.5x10.06-1.27 PRSP0016DH Index mark Rev.2.00, Feb.18.2005, page Previous Code MASS[Typ.] DP-16FV 1.05g Previous Code MASS[Typ ...

Page 11

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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