pll103-02 ETC-unknow, pll103-02 Datasheet - Page 3

• Manufacturer Part Number: pll103-02
• Description: Sdram Buffer Desktop With Dimms
• Manufacturer: ETC-unknow

I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register (1=Enable, 0=Disable)
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Receiver/Transmitter
Address Assignment
Data Transfer Rate
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
45, 44
43, 42
39, 38
34, 33
Pin#
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
48
-
-
-
A6
Provides both slave write and
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
A5
1
Default
1
0
0
0
1
1
1
1
A4
0
Description
SEL_DDR ( I2C is ready only, value is set through pin48 )
Enhanced SDRAM Drive. 1 = Enhanced 25%
Enhanced DDR Drive. 1 = Enhanced 25%
Reserved
DDR11T, DDR11C
DDR10T, DDR10C
DDR9T, DDR9C
DDR8T, DDR8C
A3
1
A2
0
A1
0
A0
1
PLL103-02
R/W
_
Rev 11/07/00 Page 3