pll102-108 PhaseLink Corp., pll102-108 Datasheet - Page 7

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pll102-108

Manufacturer Part Number
pll102-108
Description
Programmable Zero Delay Clock Driver
Manufacturer
PhaseLink Corp.
Datasheet
7. Byte 6: Buffer Drive Strength Control Register
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Strength
FBOUT
Name
-
-
-
-
-
Bit <2>
Bit <1>
Bit <0>
Default
Programmable DDR Zero Delay Clock Driver
1
1
1
1
1
0
1
1
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
These three bits will program drive strength for FBOUTT output
clock (see Table 3).
Description
PLL102-108
Rev 03/29/02 Page 7

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