mc145220 Freescale Semiconductor, Inc, mc145220 Datasheet - Page 11

• Manufacturer Part Number: mc145220
• Description: Dual Frequency Synthesizer
• Manufacturer: Freescale Semiconductor, Inc

PD out / R , PD out
Single–Ended Phase/Frequency Detector Outputs
(Pins 4 and 17)
pins are independently configured as single–ended outputs
PD out or PD out
state current–source/sink output for use as a loop error sig-
nal when combined with an external low–pass filter. The
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detector is
described below and is shown in Figure 17.
the C and C
the floating state by utilization of the standby feature in the C
or C
gain (in amps per radian) = PD out current in amps divided
by 2 .
PD out / R , Rx/ V and PD out
Double–Ended Phase/Frequency Detector Outputs
(Pins 4, 5 and 17, 16)
two pairs of pins are independently configured as double–
ended outputs R ,
these outputs can be combined externally to generate a loop
error signal. Through use of a Motorola patented technique,
the detector’s dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detectors
are described below and are shown in Figure 17.
MOTOROLA
When the C2 bits in the C or C
POL bit (C0) in the C register = low (see Figure 14)
Frequency of f V > f R or Phase of f V Leading f R : current–
Frequency of f V < f R or Phase of f V Lagging f R : current–
Frequency and Phase of f V = f R : essentially a floating
POL bit (C0) = high
Frequency of f V > f R or Phase of f V Leading f R : current–
Frequency of f V < f R or Phase of f V Lagging f R : current–
Frequency and Phase of f V = f R : essentially a floating
These outputs can be enabled, disabled, and inverted via
The phase detector gain is controllable by bits C4 and C5:
When the C2 bits in the C or C
POL bit (C0) in the C register = low (see Figure 14)
Frequency of f V > f R or Phase of f V Leading f R : V =
Frequency of f V < f R or Phase of f V Lagging f R : V =
Frequency and Phase of f V = f R : V and R remain
POL bit (C0) = high
Frequency of f V > f R or Phase of f V Leading f R : R =
Frequency of f V < f R or Phase of f V Lagging f R : R =
Frequency and Phase of f V = f R : V and R remain
i
sinking pulses from a floating state
sourcing pulses from a floating state
state; voltage at pin determined by loop filter
sourcing pulses from a floating state
sinking pulses from a floating state
state; voltage at pin determined by loop filter
negative pulses, R = essentially high
essentially high, R = negative pulses
essentially high, except for a small minimum time period
when both pulse low in phase
negative pulses, V = essentially high
essentially high, V = negative pulses
essentially high, except for a small minimum time period
when both pulse low in phase
registers (bit C6). This is a patented feature.
i
registers. If desired, these pins can be forced to
i
, respectively. As such, each pin is a three–
i
/ R
V or R
i
i
,
i
/ R
V
i
i
registers are high, these
i
i
, respectively. As such,
registers are low, these
, Rx
i
/ V
i
via C register bits C6 or C0. This is a patented feature. Note
that when disabled in standby, these outputs are forced to
their rest condition (high state). See Figure 14.
GND to V+.
LD and LD
Lock Detector Outputs (Pins 3 and 18)
very narrow low–going pulses of a few nanoseconds when
the respective loop is locked (f R and f V of the same phase
and frequency). The output pulses low when f V and f R are
out of phase or different frequencies. LD is the logical AND-
ing of R and V , while LD
and LD
during standby. If unused, LD should be tied to GND and LD
should be tied to GND
ers. This facilitates a wired–OR function. See Figure 21.
Rx/ V and Rx
External Current Setting Resistors (Pins 5 and 16)
pins are independently configured as current setting pins Rx
or Rx
these pins and GND and GND
and C5 in the C and C
current that the PD out pins sink and source. When bits C4
and C5 are both set high, the maximum current is obtained;
see Table 2 for other values of current.
follows.
where Rx is the value of external resistor in ohms, V1 is the
supply voltage, V2 is 1.5 V for a reference current through Rx
of 100 A or 1.745 V for a reference current of 200 A, and I
is the reference current flowing through Rx or Rx
plied by a factor of approximately 10 (in the 100% current
mode) and delivered by the PD out or PD out pin, respectively.
To achieve a maximum phase detector output current of
1 mA, the resistor should be about 15 k when a 3 V supply
is employed. See Table 3.
V
These outputs can be enabled, disabled, or interchanged
The R and V output signals swing from approximately
Each output is essentially at a high–impedance state with
Upon power up, on–chip initialization circuitry forces LD
These outputs have open–drain N–channel MOSFET driv-
When the C2 bits in the C or C
The formula for determining the value of Rx or Rx
The reference current flowing through Rx or Rx is multi-
i
. See Figure 17.
i
, respectively. As such, resistors tied between each of
i
to the high–impedance state. These pins are low
Voltage
Supply
i
3 V
5 V
Table 2. PD out or PD out Current
i
C5
/ V
0
0
1
1
i
Table 3. Rx Values
i
15 k
16 k
.
i
Rx
Rx =
registers, determine the amount of
i
C4
0
1
0
1
is the logical ANDing of R
V1 – V2
i
i
, in conjunction with bits C4
I
registers are low, these two
PD out or PD out
100% Mode
Current in
Current
100%
1 mA
2 mA
50%
80%
5%
MC145220
i
.
i
i
is as
and
11
i