el4511 Intersil Corporation, el4511 Datasheet
el4511
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el4511 Summary of contents
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... Data Sheet Super Sync Separator The EL4511 sync separator IC is designed for operation in the next generation of DTV, HDTV, and projector applications, as well as broadcast equipment and other applications where video signals need to be processed. The EL4511 accepts sync on green, separate sync, and H/V sync inputs, automatically selecting the relevant format ...
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... SYNCOUT Td BACKPORCH Timing Relative to BACKPORCH Input LEVEL OUTPUT DRIVER, LEVEL Amplitude of V LEVEL SYNC Z O/P Resistance of Driver Stage LEVEL 2 EL4511 = 25°C) to GND) +6V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C S +0.3V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C S Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70° ...
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... T Clock to Data Out Time CD NOTES: 1. NTSC signal; see curves for other rates. 2. XTAL pin must be low, otherwise 70µA. 3. I/P range reduces 3.3V - 4.5V (see Timing Diagram 1 EL4511 = +5V 25°C, NTSC input signal on SYNCIN, no output loads, unless CCA1 CCA2 CCD A CONDITIONS Refer to description of operation ...
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... PIN TYPE Input Crystal input (see Table 2 for details) Logic Output Vertical blank output Logic Output Indicates that the EL4511 has locked to the line rate and has found three consecutive “good H lines” Logic Input Power-down = hi Logic Input Serial interface enable = low ...
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... HORIZONTAL SYNC HIN PROCESSING POWER DOWN PDWN LOW ACTIVE SERIAL SDENB DATA ENABLE SERIAL CLOCK SCL SERIAL I/F SERIAL DATA SDA GNDA1 5 EL4511 VCCD & DIGITAL PROCESSING RESET RATE REFERENCE ACQUISITION OSCILLATOR OSCILLATOR VCCA2 GNDA2 XTALIN MODE CONTROL PINS FIGURE 3. BLOCK DIAGRAM ...
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... Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). 6 EL4511 ...
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... Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). 7 EL4511 START OF FIELD ONE 624 625 ...
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... BLANK ODD/EVEN SYNCIN 560 561 562 SYNCOUT H OUT BACKPORCH V OUT V BLANK ODD/EVEN FIGURE 6. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD 8 EL4511 DEFAULT 20 LINES ODD FIELD 563 564 565 566 567 DEFAULT 20 LINES EVEN FIELD ... ...
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... FIGURE 7. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED ODD & EVEN FIELD (1250 LINES) 9 EL4511 Default 20 Lines Default 20 Lines FN7009.7 July 21, 2005 ...
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... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 10 EL4511 = V = +5V 25°C, NO FILTER (REGISTER 2 BIT CCD A COLOR BURST V SLICE 50% V SYNC (SYNC TIP SYNC ...
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... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 11 EL4511 = V = +5V 25°C, FILTER IN (REGISTER 2 BIT CCD A COLOR BURST V SLICE 50% V SYNC (SYNC TIP SYNC ...
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... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 12 EL4511 = V = +3.3V/+5V 25°C, NO FILTER (REGISTER 2 BIT CCD A td HOUT T HOUT td BACKPORCH CONDITIONS See Timing Diagram 3 ...
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... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 13 EL4511 = V = +3.3V/+5V 25°C, FILTER (REGISTER 2 BIT CCD A td HOUT T HOUT td BACKPORCH CONDITIONS See Timing Diagram 4 ...
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Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 PINS 1 & DIGITAL OPERATING 24 XTAL, FILTER STANDARD DEFAULT XTALN ENABLED SDTV (Clean signals) 525 NTSC Yes 00 default 625 PAL Yes 00 ...
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Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 (Continued) PINS 1 & DIGITAL OPERATING 24 XTAL, FILTER STANDARD DEFAULT XTALN ENABLED 1080 I / (29/30) Yes 00 default 1080 I / (48/50) ...
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... HIN input at a TTL level. The EL4511 will continue to monitor these two signals in turn until an appropriate signal is detected. If only one of HIN and SYNCIN is enabled, the EL4511 will continuously monitor the selected signal until an appropriate signal is detected; this will give a shorter lock time where only one type of signal is used ...
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... If the vertical sync input pin, VERTIN, is enabled, the EL4511 will automatically detect whether a valid signal is present on that pin, and incorporate that signal into the algorithm. ...
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... By default, the EL4511 will wake up with Register 9, bit 6 set to Low. This will allow the use of logic levels on pins 1 & drive register1, bits 5:3 and register 2 bit 0 into the combinations shown in Table 2 ...
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... As there is no Microcontroller connected in this example, there is no need for a XTAL at pins 1 & 24. These pins can be used to force the EL4511 to select the correct operation (and speed up acquisition). Note that a Low Pas Filter is in the NTSC/PAL signal path to reduce noise, glitches and subcarrier. (In signals with bad Croma/Luma gain balance, the subcarrier can extend into the sync slicing level) (See Table 2 for details ...
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... XTALN (PIN 24) FIGURE 10. BLOCK DIAGRAM OF REFERENCE OSCILLATOR 20 EL4511 Example: Using a 32.768kHz crystal, the count period is 30.52µs. With a 20ms vertical rate, there will be approximately 656 cycles (290 Hex) in the "counts per field" registers 13 and 14. With a 16.666'ms vertical rate, the count of 546 (222 Hex) will be seen. Computer & ...
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... EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync detection, two-level sync detection and separate H/V (VGA) sync detection, respectively. Other signals used to prioritize tri-level syncs (TriLevPriority), separate H/V (Hin Priority only allow signals from HIN/VERTIN (HinVinOnly). 21 EL4511 Hin HinVin REGISTER Priority Only 0 ...
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... Number of lines before vertical sync time. 1 HIN polarity on reset if EnHpolarityDet = Lo. 1 VERTIN polarity on reset and if EnVpolarityDet = Lo. 1 Allows EL4511 to detect and set polarity on HIN. 1 Allows EL4511 to detect and set polarity on VERTIN. R/W 22h 0 Multiplexes clock onto V R Only valid if V circuit is enabled ...
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... VinSyncDet 1 VinPolarity 0 HPolarity 16 Oscillator Settings Observe 2 4 RateLocked 3 ALOS WRITE TO REGISTER OF EL4511 (WRITE INDICATED WITH ADDRESS = 0XXXXXXX) SDENB t(SCL)HI t(SCL)LO SCL SDA 0 td(SCL) START “0”=WRITE REGISTER ADDRESS 7 BITS READ FROM REGISTER OF EL4511 (READ INDICATED WITH ADDRESS = 1XXXXXXX) SDENB t(SCL)HI t(SCL)LO ...
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... As some of the signals in this application were non standard formats, the fixed slice mode is used by setting register 2, bit high. Register 1, bit 6 is also set to a high. This forced the EL4511 to provide outputs even when the input signals are not recognized by the internal algorithms. VIDEO SIGNALS (RGB) 75Ω ...