el4583a Intersil Corporation, el4583a Datasheet - Page 4

• Manufacturer Part Number: el4583a
• Description: Sync Separator, 50% Slice, S-h, Filter, Hout
• Manufacturer: Intersil Corporation

Pin Descriptions
PIN NUMBER
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Digital Ground This is the ground return for digital buffer outputs.
Detect Output
Porch Output
Vertical Sync
Filter Cut-Off
Level Output
Sync Output
Filter Output
Sync Output
Video Input
PIN NAME
Composite
Filter Input
Burst/Back
Set Detect
Odd/Even
Horizontal
No Signal
V
Ground
Analog
Output
Output
R
Level
DD
SET
5V
4
A resistor R
increases the filter 3.58MHz color burst attenuation. See the typical performance characteristics.
A resistor R
the loss of signal output on pin 10. The relationship is V
detected sync pulse amplitude applied to pin 4. See the typical performance characteristics.
This output replicates all the sync inputs on the input video.
The filter is a 3 pole active filter with a gain of 2, designed to produce a constant phase delay of nominally 260ns
with signal amplitude. Resistor RF on pin 1 controls the filter cut-off. An internal clamp sets the minimum voltage
on pin 4 at 1.55V when the input becomes low impedance. Above the clamp voltage, an input current of 1µA
charges the input coupling capacitor. With loss of signal, the current source switches to a value of 10µA, for faster
signal recovery.
The vertical sync output is synchronous with the first serration pulse rising edge in the vertical interval of the input
signal and ends on the trailing edge of the first equalizing Output pulse after the vertical interval. It will therefore
be slightly more than 3H lines wide.
Output of the active 3 pole filter which has its input on pin 4. It is recommended to ac couple the output to pin 8.
This input can be directly driven by the signal if it is desired to bypass the filter, for example, in the case of strong
clean signals. This input is 6dB less sensitive than the filter input.
This pin provides an analog voltage which is nominally equal to twice the sync pulse amplitude of the video input
signal applied to pin 4. It therefore provides an indication of signal strength.
This is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below
a predetermined amplitude as set by R
is initiated.
The start of back porch output is triggered on the trailing edge of normal H sync, and on the rising edge of
serration pulses in the vertical interval. The pulse is timed out internally to produce a one-shot output. The pulse
width is a function of R
known reference.
The current through the resistor R
include the sampling of the sync pulse 50% point, back porch output and the 2H eliminator. For faster scan rates,
the resistor needs to be reduced inversely. For NTSC 15.7kHz scan rate R
resistor.
Odd-even output is low for even field and high for odd field. The operation of this circuit has been improved for
rejecting spurious noise pulses such as those present in VCR signals.
The internal circuits are designed to have a high immunity to supply variations, although as with most I.C.s a
0.1µF decoupling capacitor is advisable.
This output produces only true H pulses of nominal width 5µs. The leading edge is triggered from the leading
edge of the input H sync, with the same prop. delay as the composite sync The half line pulses present in the
input signal during vertical blanking are eliminated with an internal 2H eliminator circuit.
This is the ground return for the signal paths in the chips, R
F
LV
connected between this input and ground determines the input filter characteristic. Increasing R
connected between pin 2 and ground determines the value of the minimum signal which triggers
SET
. This output can be used for d.c. restore functions where the back porch level is a
EL4583A
SET
LV
determines the timing of the functions within the I.C. These functions
on pin 2. There will be several horizontal lines delay before the output
PIN FUNCTION
P
MIN = 0.75RLV/R
SET
, R
F
and R
SET
LV
SET
.
, where V
is 681k 1%. R
P
MIN is the minimum
SET
must be a 1%
August 1, 2005
FN7503.1
F