mk2049-01 ETC-unknow, mk2049-01 Datasheet - Page 4

• Manufacturer Part Number: mk2049-01
• Description: Communications Clock
• Manufacturer: ETC-unknow

MDS 2049-01 J
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone]tel •www.icst.com
OPERATING MODES
The MK2049-01 has two operating modes: External and Loop Timing. Although both modes use an input
clock to generate various output clocks, there are important differences in their input requirements.
External Mode
The MK2049-01 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as
narrow as 10 ns is acceptable.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1
and E1 inputs, the CLK1 output will be the same as the input frequency, with CLK2 at twice the input
frequency. For T3 and E3 inputs, CLK1 will be 1/2 the input frequency and CLK2 will be the same as the
input frequency.
FREQUENCY LOCKING TO THE INPUT
In both modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
INPUT AND OUTPUT SYNCHRONIZATION
The rising edges of CLK1 and CLK2 do not have a fixed phase alignment with the rising edge of ICLK.
Each time the device is powered-up, the phase relationship could change. Refer to one of the other
MK2049 versions (e.g., MK2049-02, -03, -34) if input-output phase alignment is important in your
application.
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Communications Clock PLL
MK2049-01
Revision 040601