adf4360-1 Analog Devices, Inc., adf4360-1 Datasheet
adf4360-1
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adf4360-1 Summary of contents
Page 1
... Integrated Synthesizer and VCO GENERAL DESCRIPTION The ADF4360 fully integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-1 is designed for a center frequency of 2250 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF output of between 1025 MHz and 1225 MHz ...
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... ADF4360-1 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Circuit Description........................................................................... 9 Reference Input Section............................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 PFD and Charge Pump................................................................ 9 MUXOUT and Lock Detect...................................................... 10 Input Shift Register..................................................................... 10 REVISION HISTORY 12/04— ...
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... MHz/V typ 15 kHz typ Into 2.00 VSWR load. −20 dBc typ −35 dBc typ −13/−6 dBm typ Programmable steps. See Table 7. ±3 dB typ For tuned loads, see the Output Matching section. 1.25/2.5 V min/max Rev Page ADF4360-1 = 4.7 kΩ. ≤ 2 ≤ 2 ...
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... ADF4360-1 Parameter 1, 5 NOISE CHARACTERISTICS 8 VCO Phase-Noise Performance 9 Synthesizer Phase-Noise Floor 10, 11 In-Band Phase Noise 12 RMS Integrated Phase Error Spurious Signals due to PFD Frequency Level of Unlocked Signal with MTLD Enabled 1 Operating temperature range is –40°C to +85°C. 2 Guaranteed by design. Sample tested to ensure compliance. ...
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... DB22 DB2 (CONTROL BIT C2) Figure 2. Timing Diagram Rev Page ADF4360 unless otherwise noted. A MIN MAX Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time ...
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... ADF4360-1 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND GND VCO VCO DD Digital I/O Voltage to GND Analog I/O Voltage to GND REF to GND IN Operating Temperature Range Maximum Junction Temperature CSP θ Thermal Impedance JA (Paddle Soldered) ...
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... pin is 0.6 V. The relationship between I SET with a 10 µF capacitor. VCO /2 and a dc equivalent input resistance of DD must have the same value the external loop filter, which in turn drives the CP ADF4360-1 and SET ...
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... ADF4360-1 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 1 –80 –90 2 –100 –110 –120 –130 –140 –150 –160 –170 1k 10k 100k FREQUENCY OFFSET (Hz) Figure 4. Open Loop VCO Phase Noise –70 –75 –80 –85 –90 –95 –100 –105 –110 –115 – ...
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... R counter latch, ABP2 and ABP1, control the width of the pulse (see Table 9 DIVIDER HI N DIVIDER R DIVIDER N DIVIDER CP OUTPUT Figure 12. PFD Simplified Schematic and Timing (In Lock) Rev Page ADF4360 13-BIT B COUNTER LOAD PRESCALER P/P+1 LOAD 5-BIT A MODULUS COUNTER ...
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... Bits BSC1 and BSC2 in the R counter latch. Where the required PFD frequency exceeds 1 MHz, the divide ratio should be set to allow enough time for correct band selection. Rev Page Data Latch Control Latch R Counter N Counter (A and B) Test Mode Latch ) and resultant V TUNE FREQUENCY (MHz) , ADF4360-1 TUNE ...
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... RF output stage is shut down until the part achieves lock as and measured by the digital lock detect circuitry. This is enabled by the mute-till-lock detect (MTLD) bit in the control latch. DD Rev Page ADF4360 OUT OUT BUFFER/ VCO DIVIDE BY 2 Figure 15. Output Stage ADF4360-1 ...
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... ADF4360-1 LATCH STRUCTURE Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determine which latch is programmed. Table 6. Latch Structure PRESCALER CURRENT VALUE SETTING 2 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 ...
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... DIGITAL LOCK DETECT (ACTIVE HIGH DIVIDER OUTPUT DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND ADF4360-1 CONTROL BITS DB2 DB1 DB0 C2 (0) C1 (0) PC1 CORE POWER LEVEL 5mA 10mA 15mA 20mA DD ...
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... ADF4360-1 Table 8. N Counter Latch DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DIV2 CPG B13 B12 B11 B10 DIVSEL B13 B12 B11 (FUNCTION LATCH) ...
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... R3 R2 R13 R12 .......... .......... .......... .......... .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... .......... .......... .......... ADF4360-1 CONTROL BITS DB2 DB1 DB0 R1 C2 (0) C1 (1) DIVIDE RATIO Not Allowed 16380 16381 16382 16383 ...
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... VCO may not oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band and the ADF4360-1 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency ...
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... Hardware Power-Up/Power-Down If the ADF4360-1 is powered down via the hardware (using the CE pin) and powered up again without any change to the N counter register during power-down, it locks at the correct fre- quency because the part is already in the correct frequency band. The lock time depends on the value of capacitance on the C pin, which is < ...
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... ADF4360-1 CONTROL LATCH With (C2, C1) = (0, 0), the control latch is programmed. Table 7 shows the input data format for programming the control latch. Prescaler Value In the ADF4360 family, P2 and P1 in the control latch set the prescaler values. Power-Down DB21 (PD2) and DB20 (PD1) provide programmable power- down modes ...
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... R counter is by default the value used to clock the band select logic, but if this value is too high (>1 MHz), a divider can be switched on to divide the R counter output to a smaller value (see Table 9). Reserved Bits DB23 to DB22 are spare bits that are reserved. They should be programmed to 0. Rev Page ADF4360-1 ...
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... The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4360-1, which allows levels from −13 dBm to −6 dBm from each output. The RF output is designed to drive a 50 Ω load but must be ac-coupled, as shown in Figure 17. If the I and Q inputs are driven in quadrature p-p signals, the resulting output power from the modulator will be approximately 2 dBm ...
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... FIXED FREQUENCY LO Figure 18 shows the ADF4360-1 used as a fixed frequency LO at 2.2 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360 MHz. Because using a larger PFD frequency allows users to use a smaller N, the in-band phase noise is reduced to as low as possible, – ...
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... The shunt inductor needs relatively high value (>40 nH). Experiments have shown that Figure 22 provides an excellent match to 50 Ω over the operating range of the ADF4360-1. This gives approximately −4 dBm output power across the frequency range of the ADF4360-1. Both single-ended architectures can be examined using the EVAL_ADF4360-1EB1 evaluation board ...
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... Temperature Range ADF4360-1BCP −40°C to +85°C ADF4360-1BCPRL −40°C to +85°C ADF4360-1BCPRL7 −40°C to +85°C 1 ADF4360-1BCPZ −40°C to +85°C 1 ADF4360-1BCPZRL −40°C to +85°C 1 ADF4360-1BCPZRL7 −40°C to +85°C EVAL-ADF4360-1EB1 Pb-free part. 4.00 BSC SQ 0.60 MAX 0.50 BSC TOP 3.75 VIEW BSC SQ ...
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... ADF4360-1 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, provided that the system conforms to the I © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...