nb100ep223 ON Semiconductor, nb100ep223 Datasheet - Page 2

• Manufacturer Part Number: nb100ep223
• Description: 3.3v1 22 Differential Hstl/pecl To Hstl Clock Driver With Lvttl Clock Select And Output Enable
• Manufacturer: ON Semiconductor

All V
The thermally conductive exposed pad on package bottom (see package case drawing) is electrically connected to GND internally.
Table 1. PIN DESCRIPTION
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the package is electrically connected to GND internally.
HSTL_CLK*, HSTL_CLK**
LVPECL_CLK*, LVPECL_CLK**
CLK_SEL**
OE**
Q0−Q21, Q0−Q21
V
V
GND***
* Pins will default LOW when left open.
PIN
CC
CCO
CC
V
V
, V
CC0
CC0
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
CCO
, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (V
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
48
1
47
2
46
HSTL, LVPECL or LVDS Differential Inputs
LVPECL Differential Inputs
LVCMOS/LVTTL Input CLK Select
LVCMOS/LVTTL Output Enable
HSTL Differential Outputs
Positive Supply_Core (3.0 V − 3.6 V)
Positive Supply_HSTL Outputs(1.6V−2.0V)
Ground
3
FUNCTION
45
4
Figure 1. 64−Lead LQFP Pinout (Top View)
44
5
43
6
42
NB100EP223
http://onsemi.com
7
41
8
40
2
9
39
10
38
11
* The OE (Output Enable) signal is synchronized with the
rising edge of the HSTL_CLK and LVPECL_CLK signal.
37
Table 2. FUNCTION TABLE
OE*
12
H
H
L
L
36
13
CLK_SEL
35
14
H
H
L
L
34
15
33
LVPECL_CLK
16
HSTL_CLK
Q0−Q21
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
L
L
V
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
Q20
Q20
V
CC0
CC0
LVPECL_CLK
CC
HSTL_CLK
Q0−Q21
0 V
H
H
CCO
).