nb7l14m ON Semiconductor, nb7l14m Datasheet
nb7l14m
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nb7l14m Summary of contents
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... CML output structures, optimized for minimal skew and jitter. Device produces four identical output copies of clock or data operating GHz or 12 Gb/s, respectively. As such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs incorporate internal 50 W termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6) ...
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... CLK and CLK, then the device will be susceptible to self−oscillation. 2. CML outputs require 50 W receiver termination resistors Exposed Pad (EP NB7L14M Figure 2. QFN−16 Pinout (Top View) Description Internal 50 W Termination Pin for CLK ...
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Table 2. ATTRIBUTES ESD Protection Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply ...
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Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs ( (Note 5) Symbol Characteristic I Power Supply Current (Inputs and Outputs Open Output HIGH Voltage (Note Output LOW Voltage (Note 6) OL Differential Input Driven Single−Ended ...
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Table 5. AC CHARACTERISTICS (V Symbol Characteristic V Output Voltage Amplitude (@V OUTPP (See Figure 4) f Maximum Operating Data Rate data t , Propagation Delay to Output Differential PLH t PHL t Duty Cycle Skew (Note 10) SKEW Within−Device ...
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DDJ = 1.6 ps* Time (80 ps/div) Figure 4. Typical Output Waveform at 2.488 Gb/s ^23 with PRBS 2 − mV) inpp *Input signal DDJ = 6.4 ps DDJ = 2 ps*** Time (18 ps/div) Figure 6. ...
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... CLK CLK PLH Figure 8. AC Reference Measurement NB7L14M Figure 9. Typical Termination for 16 mA Output Driver and Device Evaluation (Refer to Application Notes AND8020/D and AND8173/D) CLK V th CLK V th Figure 10. Differential Input Driven Single−Ended IHmax ...
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Table 6. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC−COUPLED RSECL, LVPECL LVTTL, LVCMOS Figure 14. CML Output Structure CONNECTIONS Connect TCLK0 TCLK0 Connect V , ...
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... Application Information All NB7L14M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are PECL Driver Recommended R Values 5.0 V 290 W 3.3 V 150 W 2 ...
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... No Connect* No Connect V TCLK V REF CLK * GND Package QFN−16 QFN−16 (Pb−Free) QFN−16 QFN−16 (Pb−Free) http://onsemi.com CLK TCLK NB7L14M V TCLK 50 W CLK NB7L14M 50 W Recommended V REF V REF LVCMOS LVTTL 1.5 V † ...
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... MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 3.00 BSC D2 1.65 1.85 E 3.00 BSC E2 1.65 1.85 e 0.50 BSC K 0.20 −−− L 0.30 0.50 SOLDERING FOOTPRINT* 3.25 0.128 0.30 EXPOSED PAD 0.012 1.50 0.059 0.30 0.012 0.50 0.02 mm SCALE 10:1 inches ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB7L14M/D ...