nb7l111m ON Semiconductor, nb7l111m Datasheet - Page 10

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nb7l111m

Manufacturer Part Number
nb7l111m
Description
2.5v / 3.3v, 6.125gb/s 1 10 Differential Clock/data Driver With Cml Output
Manufacturer
ON Semiconductor
Datasheet

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Table 7. Interfacing Options
INTERFACING OPTIONS
RSECL, LVPECL
LVTTL, LVCMOS
AC-COUPLED
LVDS
CML
Connect VTCLK0, VTCLK0, VTCLK1, VTCLK1, VTSEL, VTSEL to V
Connect VTCLK0, VTCLK0 together for CLK0 input; Connect VTCLK1, VTCLK1 together for CLK1 input;
Connect VTSEL, VTSEL together for SEL control input.
Bias VTCLK0, VTCLK0, VTSEL, VTSEL and VTCLK1, VTCLK1 inputs within (VCMR) Common Mode
Range.
Standard ECL termination techniques. See AND8020.
An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V
for LVTTL and V
50 W
CC
/2 for LVCMOS inputs.
Figure 17. CML Output Structure
http://onsemi.com
V
V
NB7L111M
CC
EE
10
16 mA
CONNECTIONS
50 W
Q
Q
CC

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