nb4n11m ON Semiconductor, nb4n11m Datasheet

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nb4n11m

Manufacturer Part Number
nb4n11m
Description
3.3 V 2.5 Gb/s Multi Level Clock/data Input To Cml Receiver/ Buffer/ Translator
Manufacturer
ON Semiconductor
Datasheet

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NB4N11M
3.3 V 2.5 Gb/s Multi Level
Clock/Data Input to CML
Receiver/ Buffer/ Translator
Description
distribution/translation chip with CML output structure, targeted for
high−speed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.
(See Table 5). The CML outputs are 16 mA open collector
(See Figure 18) which requires resistor (R
termination voltage. The open collector CML outputs must be
terminated to V
current–mode logic (CML) compatible levels when receiver loaded
with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies
(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.
at www.onsemi.com.
Features
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 1
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
T h e N B 4 N 11 M i s a d i f f e r e n t i a l 1 −t o −2 c l o c k / d a t a
Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS
The device is offered in a small 8−pin TSSOP package.
Application notes, models, and support documentation are available
V
EP, and SG Devices
Maximum Input Clock Frequency > 2.5 GHz
Maximum Input Data Rate > 2.5 Gb/s
Typically 1 ps of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R
420 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Operating Range: V
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
These are Pb−Free Devices*
TT
= 1.8 V to 3.6 V
TT
at power up. Differential outputs produces
CC
= 3.0 V to 3.6 V with V
L
) load path to V
EE
= 0 V and
L
= 25 W
1
TT
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Application Note AND8002/D.
D
D
Figure 1. Functional Block Diagram
A
L
Y
W
G
(Note: Microdot may be in either location)
CASE 948R
DT SUFFIX
TSSOP−8
8
ORDERING INFORMATION
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
http://onsemi.com
Publication Order Number:
8
1
DIAGRAM*
MARKING
ALYWG
E11M
G
NB4N11M/D
Q0
Q0
Q1
Q1

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nb4n11m Summary of contents

Page 1

... EP11, LVEP11, SG11 or 7L11M devices. Device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 5) ...

Page 2

Figure 2. Pinout (Top View) and Logic Diagram Table 1. Pin Description Pin Name I CML Output 2 Q0 CML Output 3 Q1 CML Output 4 Q1 CML Output 5 ...

Page 3

Table 2. ATTRIBUTES ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply ...

Page 4

Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs Symbol Characteristic I Power Supply Current (Inputs and Outputs Open 3 2 Output HIGH Voltage (Note ...

Page 5

Table 5. AC CHARACTERISTICS V Symbol Characteristic V Output Voltage Amplitude (R OUTPP L (See Figure 12) V Output Voltage Amplitude (R OUTPP L (See Figure 12) f Maximum Operating Data Rate DATA t , Propagation Delay to Output Differential ...

Page 6

... TEMPERATURE (°C) Figure 6. Typical Propagation Delay vs. Temperature (V − 3 255C 100 mV −40 Figure 8. Supply Current vs. Temperature NB4N11M −40° 85°C 5 25°C 0 2.25 2.5 2.75 3 0.5 0.75 1 Figure 5. Data Dependent Jitter vs. Frequency = 3.3 V and Temperature ( − 255C ...

Page 7

DDJ = 5 ps TIME (266.8 ps/div) Figure 9. Typical Differential Output Waveform at 750 Mb Left Plot Right Plot DDJ = 12 ps TIME (133.2 ps/div) Figure 10. ...

Page 8

Figure 12. AC Reference Measurement Q DUT Driver Device Q Figure 13. Typical Termination for Output Driver and Device Evaluation Figure 14. Differential Input Driven Single−Ended ...

Page 9

V CC Input 1. ESD C 1. Input ESD V EE Input Input 1. ESD C 1. Input ESD Internal Current Source Figure 18. CML Input and Output Structure http://onsemi.com 9 IN ...

Page 10

... NB4N11M Figure 19. Typical Examples of the Application Interface ORDERING INFORMATION Device NB4N11MDTG NB4N11MDTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ TTB ...

Page 11

... C 0.80 1.10 0.031 0.043 D 0.05 0.15 0.002 0.006 −W− F 0.40 0.70 0.016 0.028 G 0.65 BSC 0.026 BSC K 0.25 0.40 0.010 0.016 L 4.90 BSC 0.193 BSC Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB4N11M/D ...

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