max9633ata+ Maxim Integrated Products, Inc., max9633ata+ Datasheet - Page 10

• Manufacturer Part Number: max9633ata+
• Description: Dual 36v Op Amp For 18-bit Sar Adc Front-end
• Manufacturer: Maxim Integrated Products, Inc.

Dual 36V Op Amp for 18-Bit
SAR ADC Front-End
The IC’s input common-mode range as well as the out-
put range can swing to the negative rail V
features are very important for applications where the
MAX9633 is used with a single supply (V
to ground). In such a case, being able to swing the input
common-mode to the negative rail offers ground-sensing
capability.
During normal op-amp operation, the inverting and non-
inverting inputs of the IC are at essentially the same volt-
age. However, either due to fast input voltage transients
or due to other fault conditions, these pins can be forced
to be at two different voltages.
Internal back-to-back diodes protect the inputs from an
excessive differential voltage (Figure 1). Therefore, IN+
and IN- can be any voltage within the range shown in the
Absolute Maximum Ratings. Note the protection time is
still dependent on the package thermal limits.
If the input signal is fast enough to create the internal
diode’s forward bias condition (0.7), the input signal cur-
rent must be limited to 20mA or less. If the input signal
current is not inherently limited, an external input series
resistor can be used to limit the signal input current.
Care should be taken in choosing the input series resis-
tor value, since it degrades the low-noise performance
of the device.
Figure 1. Input Protection Circuit
10
Input Common Mode and Output Swing
Input Differential Voltage Protection
EE
EE
. These two
connected
The IC has built-in circuits to protect from electrostatic
discharge (ESD) events. An ESD event produces a short,
high-voltage pulse that is transformed into a short current
pulse once it discharges through the device. The built-in
protection circuit provides a current path around the op
amp that prevents it from being damaged. The energy
absorbed by the protection circuit is dissipated as heat.
ESD protection is guaranteed up to 6kV with the Human
Body Model (HBM).
The Human Body Model simulates the ESD phenomenon
wherein a charged body directly transfers its accumu-
lated electrostatic charge to the ESD-sensitive device. A
common example of this phenomenon is when a person
accumulates static charge by walking across a carpet
and then transfers all of the charge to an ESD-sensitive
device by touching it.
The IC can operate with dual supplies from Q2.25V
to Q18V or with a single supply from +4.5V to +36V
with respect to ground. When used with dual supplies,
bypass both V
tor to ground. When used with a single supply, bypass
V
technique helps optimize performance by decreasing
the amount of stray capacitance at the op amp’s inputs
and outputs. To decrease stray capacitance, minimize
trace lengths by placing external components close to
the op amp’s pins.
For high-frequency designs, ground vias are critical to
provide a ground return path for high-frequency signals
and should be placed around the signal traces and
near the decoupling capacitors. Signal routing should
be short and direct to avoid parasitic effects. Avoid
using right angle connectors since they may introduce
a capacitive discontinuity and ultimately limit the fre-
quency response.
PROCESS: BiCMOS
CC
with a 0.1FF capacitor to ground. Careful layout
CC
Electrostatic Discharge (ESD)
and V
Power Supplies and Layout
EE
with their own 0.1FF capaci-
Chip Information