max9315eupt Maxim Integrated Products, Inc., max9315eupt Datasheet
max9315eupt
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max9315eupt Summary of contents
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Rev 1; 11/04 1:5 Differential LVPECL/LVECL/HSTL General Description The MAX9315 low-skew, 1-to-5 differential driver is designed for clock and data distribution. This device allows selection between two inputs. The selected input is reproduced at five differential outputs. The differential ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS ...............................................................................4. Inputs (CLK_, CLK_, SEL, EN ...........................................( CLK_ to CLK_ ....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA V Sink/Source Current ...
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Differential LVPECL/LVECL/HSTL DC ELECTRICAL CHARACTERISTICS (continued 2.375V to 3.8V, outputs loaded with 50Ω ± values are +3.3V IHD PARAMETER SYMBOL CONDITIONS ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS ( 2.375V to 3.8V, outputs loaded with 50Ω ± 80%), SEL = high or low low, V IHD V - ...
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Differential LVPECL/LVECL/HSTL (V = +3.3V 1V IHD CC with 50Ω 2V +25°C, unless otherwise noted SUPPLY CURRENT vs. TEMPERATURE 50 ALL PINS ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver PIN NAME 1 Q0 Noninverting Q0 Output. Typically terminate with 50Ω resistor Inverting Q0 Output. Typically terminate with 50Ω resistor Noninverting Q1 Output. Typically terminate ...
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Differential LVPECL/LVECL/HSTL V connected to ground, the outputs are LVPECL. The EE outputs are LVECL when V is connected to ground CC and V is connected to a negative supply. EE Input Bias Resistors When the inputs are open, ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver CLK CLK (CLK IS CONNECTED Figure 1. MAX9315 Switching Characteristics with Single-Ended Input CLK CLK Figure 2. MAX9315 Timing Diagram 8 _______________________________________________________________________________________ ...
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Differential LVPECL/LVECL/HSTL CLK CLK Q_ OUTPUTS ARE LOW Q_ EN Timing Diagram Figure 3. MAX9315 _______________________________________________________________________________________ Clock and Data Driver PLHD OUTPUTS STAY LOW 9 ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver V CC 75kΩ CLK0 CLK0 75kΩ 75kΩ 75kΩ CLK1 CLK1 75kΩ 75kΩ SEL ______________________________________________________________________________________ ...
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Differential LVPECL/LVECL/HSTL (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied ...